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Searched refs:IsLE (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Object/
H A DDecompressor.cpp21 bool IsLE, bool Is64Bit) { in create() argument
26 if (Error Err = D.consumeCompressedZLibHeader(Is64Bit, IsLE)) in create()
/llvm-project-15.0.7/llvm/include/llvm/Object/
H A DDecompressor.h28 bool IsLE, bool Is64Bit);
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td3620 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3621 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3622 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3623 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3624 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3625 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3627 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3628 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3629 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3630 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
[all …]
H A DMipsInstrInfo.td236 def IsLE : Predicate<"Subtarget->isLittle()">;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h640 bool &Swap, bool IsLE);
661 bool &Swap, bool IsLE);
681 unsigned &InsertAtByte, bool &Swap, bool IsLE);
H A DPPCISelLowering.cpp1824 if (IsLE) in isVPKUHUMShuffleMask()
1830 if (!IsLE) in isVPKUHUMShuffleMask()
1836 unsigned j = IsLE ? 0 : 1; in isVPKUHUMShuffleMask()
1855 if (IsLE) in isVPKUWUMShuffleMask()
1862 if (!IsLE) in isVPKUWUMShuffleMask()
1869 unsigned j = IsLE ? 0 : 2; in isVPKUWUMShuffleMask()
1896 if (IsLE) in isVPKUDUMShuffleMask()
1905 if (!IsLE) in isVPKUDUMShuffleMask()
1914 unsigned j = IsLE ? 0 : 4; in isVPKUDUMShuffleMask()
2319 if (IsLE) { in isXXSLDWIShuffleMask()
[all …]
/llvm-project-15.0.7/llvm/lib/ObjectYAML/
H A DMachOEmitter.cpp368 makeRelocationInfo(const MachOYAML::Relocation &R, bool IsLE) { in makeRelocationInfo() argument
372 if (IsLE) in makeRelocationInfo()
H A DELFEmitter.cpp1985 bool IsLE = Doc.Header.Data == ELFYAML::ELF_ELFDATA(ELF::ELFDATA2LSB); in yaml2elf() local
1988 if (IsLE) in yaml2elf()
1992 if (IsLE) in yaml2elf()
/llvm-project-15.0.7/llvm/lib/DWP/
H A DDWP.cpp283 bool IsLE = isa<object::ELF32LEObjectFile>(Obj) || in handleCompressedSection() local
287 Expected<Decompressor> Dec = Decompressor::create(Name, Contents, IsLE, Is64); in handleCompressedSection()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMPredicates.td220 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
H A DARMInstrThumb.td1635 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1637 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1639 Requires<[IsThumb, IsThumb1Only, IsLE]>;
H A DARMInstrNEON.td2462 let Predicates = [IsLE,HasNEON] in {
2487 let Predicates = [IsLE,HasNEON] in {
7522 let Predicates = [IsLE,HasNEON] in {
8016 let Predicates = [HasNEON,IsLE] in {
8041 let Predicates = [HasNEON,IsLE] in {
H A DARMInstrMVE.td7299 let Predicates = [HasMVEInt, IsLE] in {
7458 let Predicates = [IsLE,HasMVEInt] in {
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td2680 let Predicates = [IsLE] in {
2694 let Predicates = [IsLE] in {
2826 let Predicates = [IsLE] in {
2847 let Predicates = [IsLE] in {
3015 let Predicates = [IsLE] in {
3033 let Predicates = [IsLE] in {
3356 let Predicates = [IsLE] in {
3455 let Predicates = [IsLE] in {
3482 let Predicates = [IsLE] in {
3598 let Predicates = [IsLE] in {
[all …]
H A DAArch64SVEInstrInfo.td2340 let Predicates = [IsLE] in {
2641 let Predicates = [IsLE] in {
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp677 bool IsLE = DAG.getDataLayout().isLittleEndian(); in SimplifyMultipleUseDemandedBits() local
702 unsigned EltOffset = IsLE ? i : (Scale - 1 - i); in SimplifyMultipleUseDemandedBits()
719 if (IsLE && (NumSrcEltBits % NumDstEltBits) == 0) { in SimplifyMultipleUseDemandedBits()
833 if (IsLE && DemandedElts == 1 && in SimplifyMultipleUseDemandedBits()
1078 bool IsLE = TLO.DAG.getDataLayout().isLittleEndian(); in SimplifyDemandedBits() local
2247 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2284 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2334 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2503 unsigned EltOffset = IsLE ? i : (Scale - 1 - i); in SimplifyDemandedBits()
2832 bool IsLE = TLO.DAG.getDataLayout().isLittleEndian(); in SimplifyDemandedVectorElts() local
[all …]
H A DSelectionDAG.cpp3097 bool IsLE = getDataLayout().isLittleEndian(); in computeKnownBits() local
3116 unsigned Shifts = IsLE ? i : SubScale - 1 - i; in computeKnownBits()
3136 unsigned Shifts = IsLE ? i : NumElts - 1 - i; in computeKnownBits()
4025 bool IsLE = getDataLayout().isLittleEndian(); in ComputeNumSignBits() local
4045 SubOffset = (IsLE ? ((Scale - 1) - SubOffset) : SubOffset); in ComputeNumSignBits()
5622 bool IsLE = getDataLayout().isLittleEndian(); in FoldConstantArithmetic() local
5626 if (BV1->getConstantRawBits(IsLE, EltBits, RawBits1, UndefElts1) && in FoldConstantArithmetic()
5627 BV2->getConstantRawBits(IsLE, EltBits, RawBits2, UndefElts2) && in FoldConstantArithmetic()
5641 BuildVectorSDNode::recastRawBits(IsLE, BVVT.getScalarSizeInBits(), in FoldConstantArithmetic()
H A DDAGCombiner.cpp13940 bool IsLE = DAG.getDataLayout().isLittleEndian(); in ConstantFoldBITCASTofBUILD_VECTOR() local
13941 if (!BVN->getConstantRawBits(IsLE, DstBitSize, RawBits, UndefElements)) in ConstantFoldBITCASTofBUILD_VECTOR()
17995 bool IsLE = DAG.getDataLayout().isLittleEndian(); in mergeStoresOfConstantsOrVecElts() local
17997 unsigned Idx = IsLE ? (NumStores - 1 - i) : i; in mergeStoresOfConstantsOrVecElts()
19842 bool IsLE = DAG.getDataLayout().isLittleEndian(); in visitEXTRACT_VECTOR_ELT() local
19845 unsigned BCTruncElt = IsLE ? 0 : NumElts - 1; in visitEXTRACT_VECTOR_ELT()
19859 BCTruncElt = IsLE ? 0 : XBitWidth / VecEltBitWidth - 1; in visitEXTRACT_VECTOR_ELT()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp15418 bool IsLE = getTarget().isLittleEndian(); in EmitPPCBuiltinExpr() local
15425 if (!IsLE) in EmitPPCBuiltinExpr()
15445 Op0 = IsLE ? HiLd : LoLd; in EmitPPCBuiltinExpr()
15446 Op1 = IsLE ? LoLd : HiLd; in EmitPPCBuiltinExpr()
15450 if (IsLE) { in EmitPPCBuiltinExpr()
15472 bool IsLE = getTarget().isLittleEndian(); in EmitPPCBuiltinExpr() local
15479 if (IsLE) { in EmitPPCBuiltinExpr()
15516 if (IsLE && Width > 1) { in EmitPPCBuiltinExpr()
15529 Result = StoreSubVec(8, NumBytes - 8, IsLE ? 0 : 1); in EmitPPCBuiltinExpr()
15535 IsLE ? (Stored >> 2) : 3 - (Stored >> 2)); in EmitPPCBuiltinExpr()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp7632 bool IsLE = SI.getModule()->getDataLayout().isLittleEndian(); in splitMergedValStore() local
7639 const bool IsOffsetStore = (IsLE && Upper) || (!IsLE && !Upper); in splitMergedValStore()