677   bool IsLE = DAG.getDataLayout().isLittleEndian();  in SimplifyMultipleUseDemandedBits()  local
702         unsigned EltOffset = IsLE ? i : (Scale - 1 - i);  in SimplifyMultipleUseDemandedBits()
719     if (IsLE && (NumSrcEltBits % NumDstEltBits) == 0) {  in SimplifyMultipleUseDemandedBits()
833     if (IsLE && DemandedElts == 1 &&  in SimplifyMultipleUseDemandedBits()
1078   bool IsLE = TLO.DAG.getDataLayout().isLittleEndian();  in SimplifyDemandedBits()  local
2247       if (IsLE && IsVecInReg && DemandedElts == 1 &&  in SimplifyDemandedBits()
2284       if (IsLE && IsVecInReg && DemandedElts == 1 &&  in SimplifyDemandedBits()
2334     if (IsLE && IsVecInReg && DemandedElts == 1 &&  in SimplifyDemandedBits()
2503         unsigned EltOffset = IsLE ? i : (Scale - 1 - i);  in SimplifyDemandedBits()
2523     } else if (IsLE && (NumSrcEltBits % BitWidth) == 0) {  in SimplifyDemandedBits()
2832   bool IsLE = TLO.DAG.getDataLayout().isLittleEndian();  in SimplifyDemandedVectorElts()  local
2908       if (IsLE) {  in SimplifyDemandedVectorElts()
3264     if (IsLE && Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG &&  in SimplifyDemandedVectorElts()
3279       if (IsLE && DemandedSrcElts == 1 && Src.getOpcode() == ISD::AND &&  in SimplifyDemandedVectorElts()