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Searched refs:CreateReg (Results 1 – 25 of 71) sorted by relevance

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/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DMachineInstrTest.cpp141 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); in TEST()
143 MachineOperand::CreateReg(VirtualReg, /*isDef*/ false)); in TEST()
147 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); in TEST()
149 MachineOperand::CreateReg(VirtualReg, /*isDef*/ false)); in TEST()
153 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); in TEST()
159 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); in TEST()
161 MachineOperand::CreateReg(SentinelReg, /*isDef*/ true)); in TEST()
165 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); in TEST()
171 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); in TEST()
211 MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true)); in TEST()
[all …]
H A DMachineOperandTest.cpp67 MachineOperand MO = MachineOperand::CreateReg( in TEST()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrBuilder.h69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false, in getFullAddress()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false, in getFullAddress()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIFixVGPRCopies.cpp59 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp212 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); in runOnMachineFunction()
219 MI.addOperand(MachineOperand::CreateReg( in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTOCRegDeps.cpp121 MI.addOperand(MachineOperand::CreateReg(TOCReg, in processBlock()
H A DPPCPreEmitPeephole.cpp338 MachineOperand::CreateReg(Pair->UseReg, true, true); in addLinkerOpt()
340 MachineOperand::CreateReg(Pair->UseReg, false, true); in addLinkerOpt()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp218 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
248 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
H A DARMBaseInstrInfo.h544 MachineOperand::CreateReg(PredReg, false)}};
550 return MachineOperand::CreateReg(CCReg, false);
557 return MachineOperand::CreateReg(ARM::CPSR,
H A DARMSLSHardening.cpp332 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/, in ConvertIndirectCallToIndirectJump()
H A DThumb2InstrInfo.cpp581 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
613 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp644 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in addStackMapLiveVars()
692 Ops.push_back(MachineOperand::CreateReg( in selectStackmap()
803 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true)); in selectPatchpoint()
852 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
858 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
871 Ops.push_back(MachineOperand::CreateReg( in selectPatchpoint()
877 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true, in selectPatchpoint()
905 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayCustomEvent()
907 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)), in selectXRayCustomEvent()
1234 Op = MachineOperand::CreateReg(Reg, false); in selectIntrinsicCall()
[all …]
H A DFunctionLoweringInfo.cpp371 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { in CreateReg() function in FunctionLoweringInfo
396 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DLiveVariables.cpp244 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
256 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
267 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
380 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
397 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
H A DMachineOutliner.cpp845 MachineOperand::CreateReg(I, true, /* isDef = true */ in outline()
851 MachineOperand::CreateReg(I, false, /* isDef = false */ in outline()
H A DMachineInstr.cpp91 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true)); in addImplicitDefUseOperands()
95 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true)); in addImplicitDefUseOperands()
1879 addOperand(MachineOperand::CreateReg(IncomingReg, in addRegisterKilled()
1946 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDead()
1983 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDefined()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp471 Ldst.addOperand(MachineOperand::CreateReg(NewBase, true)); in changeToAddrMode()
474 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DFunctionLoweringInfo.h202 Register CreateReg(MVT VT, bool isDivergent = false);
/llvm-project-15.0.7/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp200 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anon37a612fe0111::MSP430Operand
461 Operands.push_back(MSP430Operand::CreateReg(RegNo, StartLoc, EndLoc)); in ParseOperand()
/llvm-project-15.0.7/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp212 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anonc58108e20111::AVROperand
414 Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc())); in tryParseRegisterOperand()
/llvm-project-15.0.7/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp599 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anone15613a60211::VEOperand
1471 Operands.push_back(VEOperand::CreateReg(RegNo1, S1, E1)); in parseOperand()
1472 Operands.push_back(VEOperand::CreateReg(RegNo2, S2, E2)); in parseOperand()
1530 Op = VEOperand::CreateReg(RegNo, S, E); in parseVEAsmOperand()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SLSHardening.cpp369 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/, in ConvertBLRToBL()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp85 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
91 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp367 addNodeIDMachineOperand(MachineOperand::CreateReg(Reg, false)); in addNodeIDRegType()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp452 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg() function in __anon07e578c20211::SparcOperand
1059 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); in parseOperand()
1119 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); in parseSparcAsmOperand()

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