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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2 |
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| #
06943537 |
| 09-Feb-2022 |
serge-sans-paille <[email protected]> |
Cleanup MCParser headers
As usual with that header cleanup series, some implicit dependencies now need to
be explicit:
llvm/MC/MCParser/MCAsmParser.h no longer includes llvm/MC/MCParser/MCAsmLexer.
Cleanup MCParser headers
As usual with that header cleanup series, some implicit dependencies now need to
be explicit:
llvm/MC/MCParser/MCAsmParser.h no longer includes llvm/MC/MCParser/MCAsmLexer.h
Preprocessed lines to build llvm on my setup:
after: 1068185081
before: 1068324320
So no compile time benefit to expect, but we still get the looser coupling
between files which is great.
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D119359
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Revision tags: llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2 |
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| #
f3a344d2 |
| 07-Jan-2022 |
Kazu Hirata <[email protected]> |
[Target] Remove redundant member initialization (NFC)
Identified with readability-redundant-member-init.
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| #
e5947760 |
| 03-Jan-2022 |
Kazu Hirata <[email protected]> |
Revert "[llvm] Remove redundant member initialization (NFC)"
This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.
This patch causes gcc to issue a lot of warnings like:
warning: base cl
Revert "[llvm] Remove redundant member initialization (NFC)"
This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.
This patch causes gcc to issue a lot of warnings like:
warning: base class ‘class llvm::MCParsedAsmOperand’ should be
explicitly initialized in the copy constructor [-Wextra]
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fd480888 |
| 02-Jan-2022 |
Kazu Hirata <[email protected]> |
[llvm] Remove redundant member initialization (NFC)
Identified with readability-redundant-member-init.
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9d20fa09 |
| 05-Dec-2021 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support VE specific data directives in MC
Support VE specific data directives, .word/.long/.llong, in MC layer.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D115120
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Revision tags: llvmorg-13.0.1-rc1 |
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| #
89b57061 |
| 08-Oct-2021 |
Reid Kleckner <[email protected]> |
Move TargetRegistry.(h|cpp) from Support to MC
This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually us
Move TargetRegistry.(h|cpp) from Support to MC
This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually use the target, so we might as well move this out of Support.
This allows us to ensure that Support doesn't have includes from MC/*.
Differential Revision: https://reviews.llvm.org/D111454
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Revision tags: llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1 |
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| #
79429601 |
| 28-Oct-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Add vector mask operation instructions
Add VFMK/VFMS/VFMF/ANDM/ORM/XORM/EQVM/NNDM/NEGM/PCVM/LZVM/TOVM
isntructions. Add regression tests too. Also add new patterns
to parse VFMK/VFMS/VFMF mne
[VE] Add vector mask operation instructions
Add VFMK/VFMS/VFMF/ANDM/ORM/XORM/EQVM/NNDM/NEGM/PCVM/LZVM/TOVM
isntructions. Add regression tests too. Also add new patterns
to parse VFMK/VFMS/VFMF mnemonics.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D90297
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| #
cbdee7df |
| 28-Oct-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Add vector merger operation instructions
Add VMRG/VSHF/VCP/VEX isntructions. Add regression tests too.
Also add new patterns to parse new UImm4 oeprand.
Reviewed By: simoll
Differential Revi
[VE] Add vector merger operation instructions
Add VMRG/VSHF/VCP/VEX isntructions. Add regression tests too.
Also add new patterns to parse new UImm4 oeprand.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D90292
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c5fa6bae |
| 26-Oct-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Add vector float instructions
Add VFAD/VFSB/VFMP/VFDV/VFSQRT/VFCP/VFCM/VFMAD/VFMSB/VFNMAD/VFNMSB/
VRCP/VRSQRT/VRSQRTNEX/VFIX/VFIXX/VFLT/VFLTX/VCVS/VCVD instructions.
Add regression tests too.
[VE] Add vector float instructions
Add VFAD/VFSB/VFMP/VFDV/VFSQRT/VFCP/VFCM/VFMAD/VFMSB/VFNMAD/VFNMSB/
VRCP/VRSQRT/VRSQRTNEX/VFIX/VFIXX/VFLT/VFLTX/VCVS/VCVD instructions.
Add regression tests too. Also add additional AsmParser for VFIX
and VFIXX instructions to parse their mnemonic.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D90166
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| #
9d0db405 |
| 26-Oct-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Add vector shift instructions
Add VSLL/VSLD/VSRL/VSLA/VSLAX/VSRA/VSRAX/VSFA instructionss. Add
additonal AsmParser for VSLD special operand. Also add regression
tests.
Reviewed By: simoll
D
[VE] Add vector shift instructions
Add VSLL/VSLD/VSRL/VSLA/VSLAX/VSRA/VSRAX/VSFA instructionss. Add
additonal AsmParser for VSLD special operand. Also add regression
tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D90143
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| #
f2fd4209 |
| 18-Oct-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Add VBRD/VMV instructions
Add VBRD/VMV vector instructions. In order to do that, also support
VM512 registers and RV instruction format in MC layer. Also add
regression tests for new instruct
[VE] Add VBRD/VMV instructions
Add VBRD/VMV vector instructions. In order to do that, also support
VM512 registers and RV instruction format in MC layer. Also add
regression tests for new instructions.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D89641
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| #
7a09aec8 |
| 15-Oct-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Add LSV/LVS/LVM/SVM instructions
Add LSV/LVS/LVM/SVM vector instructions and regression tests.
Also update AsmParser to support new format of operands.
Reviewed By: simoll
Differential Revisi
[VE] Add LSV/LVS/LVM/SVM instructions
Add LSV/LVS/LVM/SVM vector instructions and regression tests.
Also update AsmParser to support new format of operands.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D89499
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Revision tags: llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3 |
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| #
fa1fecc7 |
| 06-Jul-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support symbol with offset in assembly
Summary:
Change MCExpr to support Aurora VE's modifiers. Change asmparser to use
existing MCExpr parser (parseExpression) to parse an expression continin
[VE] Support symbol with offset in assembly
Summary:
Change MCExpr to support Aurora VE's modifiers. Change asmparser to use
existing MCExpr parser (parseExpression) to parse an expression contining
symbols with modifiers and offsets. Also add several regression tests
of MC layer.
Reviewers: simoll, k-ishizaka
Reviewed By: simoll
Subscribers: hiraditya, llvm-commits
Tags: #llvm, #ve
Differential Revision: https://reviews.llvm.org/D83170
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Revision tags: llvmorg-10.0.1-rc2 |
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| #
e026f147 |
| 15-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support relocation information in MC layer
Summary:
Change VEAsmParser to support identification with relocation information
in assmebler. Change VEAsmBackend to support relocation information
[VE] Support relocation information in MC layer
Summary:
Change VEAsmParser to support identification with relocation information
in assmebler. Change VEAsmBackend to support relocation information in
MC layer. Change VEDisassembler and VEMCCodeEmitter to support binary
generation of branch target operands. Add REFLONG fixup and variant kind
to support new R_VE_REFLONG ELF symbol. And, add regression test in both
MC and CodeGen to check binary genaration with relocation information.
Differential Revision: https://reviews.llvm.org/D81553
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| #
34fef0c9 |
| 10-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support convert instructions in MC layer
Summary:
Add CVTSQ/CVTDQ/CVTQD/CVTQS instructions. Add regression tests for
them and other convert instructions of asmparser, mccodeemitter, and
disass
[VE] Support convert instructions in MC layer
Summary:
Add CVTSQ/CVTDQ/CVTQD/CVTQS instructions. Add regression tests for
them and other convert instructions of asmparser, mccodeemitter, and
disassembler. In order to add those instructions, support RD operands
in asmparser, mccodeemitter, and disassembler.
Differential Revision: https://reviews.llvm.org/D81536
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| #
b641c9f7 |
| 09-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support rest of load/store instructions in MC layer
Summary:
Add DLD/DLDU/DLDL/PFCH/TS1AM/TS2AM/TS3AM/ATMAM/CAS instructions newly.
Add regression tests for them to asmparser, mccodeemitter, an
[VE] Support rest of load/store instructions in MC layer
Summary:
Add DLD/DLDU/DLDL/PFCH/TS1AM/TS2AM/TS3AM/ATMAM/CAS instructions newly.
Add regression tests for them to asmparser, mccodeemitter, and disassembler.
In order to add those instructions, change asmparser to support UImm0to2 and
UImm1 operands, add new decode functions to disassembler, and add new print
functions to instprinter.
Differential Revision: https://reviews.llvm.org/D81454
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| #
e9eafb7b |
| 09-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support Transfer Control Instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
transfer control instructions. Add FENCEI/FENCEM/FENCEC/SVOB i
[VE] Support Transfer Control Instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
transfer control instructions. Add FENCEI/FENCEM/FENCEC/SVOB instructions
also. Add new instruction format to represent FENCE* instructions too.
Differential Revision: https://reviews.llvm.org/D81440
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| #
b60404a6 |
| 08-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support floating-point arithmetic instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
floating-point arithmetic instructions. Add FADDQ, FS
[VE] Support floating-point arithmetic instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
floating-point arithmetic instructions. Add FADDQ, FSUBQ, FMULQ, and
FCMPQ instructions and F128 register class too.
Differential Revision: https://reviews.llvm.org/D81386
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| #
c95ba11a |
| 08-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support control instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
control instructions. Add not defined LPM/SPM/LFR/SFR/SMIR/NOP/LCR/
SCR
[VE] Support control instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
control instructions. Add not defined LPM/SPM/LFR/SFR/SMIR/NOP/LCR/
SCR/TSCR/FIDCR control isntructions newly. Define MISC registers which
SMIR instruction reads and IC register which SIC instruction reads.
Change asmparser to support Zero, UImm3, and UImm6 operands and MISC
registers. Change instprinter to support MISC registers also.
Change to use auto to receive dyn_cast also.
Differential Revision: https://reviews.llvm.org/D81370
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385adc47 |
| 08-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support shift operation instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
shift operation instructions. Also change asmparser to support U
[VE] Support shift operation instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
shift operation instructions. Also change asmparser to support UImm7
operand. And, add new SLD/SRD/SLA instructions also.
Differential Revision: https://reviews.llvm.org/D81324
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8948eab2 |
| 05-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support logical operation instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
logical operation instructions. Also change asmparser to suppo
[VE] Support logical operation instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
logical operation instructions. Also change asmparser to support CMOV
instruction. And, add new EQV/MRG/NND isntructions also.
Differential Revision: https://reviews.llvm.org/D81219
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117c0d7c |
| 05-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support branch instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
branch instructions. In order to support them, we enhance asmparser
by a
[VE] Support branch instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
branch instructions. In order to support them, we enhance asmparser
by adding splitting mnemonic mechanism, e.g. "bgt.l.t" into "b", "gt",
and ".l.t", and parsing mechanism for AS style memory addressing.
We also implment encoding and decoding mechanism for branch instructions.
Differential Revision: https://reviews.llvm.org/D81215
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58b810b5 |
| 05-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support fixed-point operation instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
fixed-point operation instructions. In order to support t
[VE] Support fixed-point operation instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
fixed-point operation instructions. In order to support them, we add
MImm parser to asmparser. Also add a new MPD instruction which is one
of multiply instructions.
Differential Revision: https://reviews.llvm.org/D81207
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ec2e9ce7 |
| 02-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support I32/F32 registers in assembler parser
Summary:
Support I32/F32 registers in assembler parser and add regression tests of LD/ST
instructions.
Differential Revision: https://reviews.llvm
[VE] Support I32/F32 registers in assembler parser
Summary:
Support I32/F32 registers in assembler parser and add regression tests of LD/ST
instructions.
Differential Revision: https://reviews.llvm.org/D80777
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| #
0e0907fa |
| 29-May-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Implements minimum MC layer for VE (4/4)
Summary:
This patch includes following items.
- Adds AsmParser and minimum AsmBackend/ELFObjectWriter/MCCodeEmitter to
support only LEA instruction
[VE] Implements minimum MC layer for VE (4/4)
Summary:
This patch includes following items.
- Adds AsmParser and minimum AsmBackend/ELFObjectWriter/MCCodeEmitter to
support only LEA instruction in order to reduce the size of this patch.
- Adds regression test of MC layer for a LEA instruction.
- Relocations are not supported this time to reduce the size of this patch.
Differential Revision: https://reviews.llvm.org/D79546
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