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Searched refs:printReg (Results 1 – 25 of 90) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp252 dbgs() << "Dest: " << printReg(Element.DestReg, TRI) in dump()
485 dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI); in dump()
535 dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI); in dump()
854 << "): In:" << printReg(getBBSelectRegIn(), TRI) in print()
855 << " Out:" << printReg(getBBSelectRegOut(), TRI) << " {"; in print()
857 OS << printReg(LI, TRI) << " "; in print()
1469 LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " in shrinkPHI()
1511 LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " in replacePHI()
1561 LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " in replaceEntryPHI()
1991 LLVM_DEBUG(dbgs() << "LiveOut: " << printReg(LI, TRI)); in rewriteLiveOutRegs()
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H A DSIOptimizeVGPRLiveRange.cpp257 LLVM_DEBUG(dbgs() << "Excluding " << printReg(MOReg, TRI) in collectCandidateRegisters()
286 LLVM_DEBUG(dbgs() << "Excluding " << printReg(Reg, TRI) in collectCandidateRegisters()
387 << printReg(MOReg, TRI, 0, MRI) << '\n'); in collectWaterfallCandidateRegisters()
391 << printReg(MOReg, TRI, 0, MRI) << '\n'); in collectWaterfallCandidateRegisters()
505 LLVM_DEBUG(dbgs() << "Optimizing " << printReg(Reg, TRI) << '\n'); in optimizeLiveRange()
548 LLVM_DEBUG(dbgs() << "Optimizing " << printReg(Reg, TRI) << '\n'); in optimizeWaterfallLiveRange()
H A DGCNNSAReassign.cpp321 << " " << llvm::printReg((VRM->getPhys(LI->reg())), TRI); in runOnMachineFunction()
359 << llvm::printReg((VRM->getPhys(Intervals.front()->reg())), TRI) in runOnMachineFunction()
361 << llvm::printReg((VRM->getPhys(Intervals.back()->reg())), TRI) in runOnMachineFunction()
H A DGCNRegPressure.cpp39 dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo()) in printLivesAt()
439 dbgs() << " " << printReg(P.first, TRI) in reportMismatch()
444 dbgs() << " " << printReg(P.first, TRI) in reportMismatch()
455 dbgs() << " " << printReg(P.first, TRI) in reportMismatch()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp138 << " " << printReg(r, TRI)); in AggressiveAntiDepBreaker()
317 dbgs() << header << printReg(Reg, TRI); in HandleLastUse()
333 dbgs() << header << printReg(Reg, TRI); in HandleLastUse()
371 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in PrescanInstruction()
392 << printReg(AliasReg, TRI) << ")"); in PrescanInstruction()
466 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in ScanInstruction()
501 LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI)); in ScanInstruction()
504 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); in ScanInstruction()
578 dbgs() << " " << printReg(r, TRI); in FindSuitableFreeRegisters()
656 LLVM_DEBUG(dbgs() << " " << printReg(NewReg, TRI)); in FindSuitableFreeRegisters()
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H A DRegAllocFast.cpp425 LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) in spill()
426 << " in " << printReg(AssignedReg, TRI)); in spill()
485 << printReg(PhysReg, TRI) << '\n'); in reload()
616 LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':'); in freePhysReg()
649 << printReg(PhysReg, TRI) << '\n'); in calcSpillCost()
701 << printReg(PhysReg, TRI) << '\n'); in assignVirtToPhysReg()
757 LLVM_DEBUG(dbgs() << "Search register for " << printReg(VirtReg) in allocVirtReg()
759 << " with hint " << printReg(Hint0, TRI) << '\n'); in allocVirtReg()
882 << printReg(PrevReg, TRI) << '\n'); in defineLiveThroughVirtReg()
922 LLVM_DEBUG(dbgs() << "In def of " << printReg(VirtReg, TRI) in defineVirtReg()
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H A DLiveRegMatrix.cpp105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg(), TRI) << " to " in assign()
106 << printReg(PhysReg, TRI) << ':'); in assign()
123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg(), TRI) in unassign()
124 << " from " << printReg(PhysReg, TRI) << ':'); in unassign()
H A DFixupStatepointCallerSaved.cpp149 << printReg(Reg, &TRI) << " -> " << printReg(SrcReg, &TRI) in performCopyPropagation()
261 << printReg(Reg, &TRI) << " at " in getFrameIndex()
292 << printReg(Reg, &TRI) << " at landing pad " in getFrameIndex()
394 LLVM_DEBUG(dbgs() << "Will spill " << printReg(Reg, &TRI) << " at index " in findRegistersToSpill()
415 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, &TRI) << " to FI " << FI in spillRegisters()
459 LLVM_DEBUG(dbgs() << "Reloading " << printReg(Reg, &TRI) << " from FI " in insertReloads()
H A DRegAllocGreedy.cpp407 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " in tryAssign()
439 << printReg(PrevReg, TRI) << " to " in canReassign()
440 << printReg(PhysReg, TRI) << '\n'); in canReassign()
455 LLVM_DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI) in evictInterference()
531 dbgs() << printReg(PhysReg, TRI) << " would clobber CSR " in canAllocatePhysReg()
1083 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = "; in calculateRegionSplitCost()
1595 LLVM_DEBUG(dbgs() << ' ' << printReg(LREdit.get(I))); in tryLocalSplit()
1805 << printReg(PhysReg, TRI) << '\n'); in tryLastChanceRecoloring()
1864 << printReg(PhysReg, TRI) << '\n'); in tryLastChanceRecoloring()
2110 << '(' << printReg(PhysReg, TRI) << ")\n"); in tryHintRecoloring()
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H A DRegAllocBase.cpp186 LLVM_DEBUG(dbgs() << "Enqueuing " << printReg(Reg, TRI) << '\n'); in enqueue()
189 LLVM_DEBUG(dbgs() << "Not enqueueing " << printReg(Reg, TRI) in enqueue()
H A DRegisterScavenging.cpp269 LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI) in FindUnusedReg()
542 dbgs() << "Removing " << printReg(SI.Reg, TRI) << in scavengeRegister()
563 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n"); in scavengeRegister()
580 << printReg(SReg, TRI) << "\n"); in scavengeRegister()
602 LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) in scavengeRegisterBackwards()
620 LLVM_DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI) in scavengeRegisterBackwards()
H A DMachineSSAContext.cpp44 Out << printReg(Value, MRI->getTargetRegisterInfo(), 0, MRI); in print()
H A DAllocationOrder.cpp43 dbgs() << ' ' << printReg(Hints[I], TRI); in create()
H A DRegisterCoalescer.cpp693 LLVM_DEBUG(dbgs() << "Extending: " << printReg(IntB.reg(), TRI)); in adjustCopiesBackFrom()
1994 << printReg(CP.getSrcReg(), TRI) << " with " in joinCopy()
2016 dbgs() << printReg(CP.getDstReg()) << " in " in joinCopy()
2018 << printReg(CP.getSrcReg()) << " in " in joinCopy()
2021 dbgs() << printReg(CP.getSrcReg(), TRI) << " in " in joinCopy()
2022 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'; in joinCopy()
2129 dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx()) in joinCopy()
2133 dbgs() << printReg(CP.getDstReg(), TRI); in joinCopy()
2999 LLVM_DEBUG(dbgs() << "\t\ttaints local " << printReg(Other.Reg) << ':' in taintExtent()
3983 LLVM_DEBUG(dbgs() << "Apply terminal rule for: " << printReg(DstReg) in applyTerminalRule()
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H A DMachineRegisterInfo.cpp222 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
231 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
237 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
243 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
H A DTargetRegisterInfo.cpp95 dbgs() << "Error: Super register " << printReg(*SR, this) in checkAllSuperRegsMarked()
96 << " of reserved register " << printReg(Reg, this) in checkAllSuperRegsMarked()
111 Printable printReg(Register Reg, const TargetRegisterInfo *TRI, in printReg() function
672 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n"; in dumpReg()
H A DRenameIndependentSubregs.cpp137 LLVM_DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses() in INITIALIZE_PASS_DEPENDENCY()
139 LLVM_DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:"); in INITIALIZE_PASS_DEPENDENCY()
145 LLVM_DEBUG(dbgs() << ' ' << printReg(NewVReg)); in INITIALIZE_PASS_DEPENDENCY()
H A DRegisterUsageInfo.cpp95 OS << printReg(PReg, TRI) << " "; in print()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFixCortexA57AES1742098Pass.cpp313 << printReg(MOp.getReg(), TRI) << "\n"); in analyzeMF()
329 << printReg(MOp.getReg(), TRI) << "\n"); in analyzeMF()
337 << printReg(MOp.getReg(), TRI) << "\n"); in analyzeMF()
355 << printReg(MOp.getReg(), TRI) << "\n"); in analyzeMF()
371 << printReg(MOp.getReg(), TRI) << ": " << *DefMI); in analyzeMF()
405 LLVM_DEBUG(dbgs() << "Inserting VORRq of " << printReg(RegToFixup, TRI) in insertAESFixup()
H A DMVETPAndVPTOptimisationsPass.cpp780 << "Replacing all uses of '" << printReg(Result) in ReduceOldVCCRValueUses()
781 << "' with '" << printReg(LastVPNOTResult) << "'\n"); in ReduceOldVCCRValueUses()
790 LLVM_DEBUG(dbgs() << "Replacing use of '" << printReg(VCCRValue) in ReduceOldVCCRValueUses()
791 << "' with '" << printReg(LastVPNOTResult) in ReduceOldVCCRValueUses()
804 << printReg(OppositeVCCRValue) << "' with '" in ReduceOldVCCRValueUses()
805 << printReg(LastVPNOTResult) << " for instr: "; in ReduceOldVCCRValueUses()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp543 LLVM_DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n"); in colorChain()
617 << printReg(DestReg, TRI) << " at " << *MI); in scanInstruction()
637 << printReg(AccumReg, TRI) << " in MI " << *MI); in scanInstruction()
663 << printReg(DestReg, TRI) << "\n"); in scanInstruction()
691 LLVM_DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI) in maybeKillChain()
703 << printReg(I->first, TRI) << "\n"); in maybeKillChain()
H A DAArch64PBQPRegAlloc.cpp249 LLVM_DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI) in addInterChainConstraint()
250 << " to " << printReg(Rd, TRI) << '\n';); in addInterChainConstraint()
255 LLVM_DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI) in addInterChainConstraint()
342 LLVM_DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at "; in apply()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp193 OS << ' ' << printReg(R, P.TRI); in operator <<()
434 OS << printReg(*I, P.TRI); in operator <<()
487 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI) in operator <<()
586 dbgs() << " " << printReg(I.first, HRI) << ":\n"; in dump_map()
787 dbgs() << __func__ << ": " << printReg(VR, HRI) in findRecordInsertForms()
852 dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n"; in findRecordInsertForms()
857 dbgs() << " (" << printReg(J.first, HRI) << ",@" << J.second << ')'; in findRecordInsertForms()
902 dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI) in findRecordInsertForms()
903 << ',' << printReg(InsR, HRI) << ",#" << L << ",#" in findRecordInsertForms()
1523 dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n"; in runOnMachineFunction()
H A DHexagonGenPredicate.cpp80 return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S); in operator <<()
226 LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.R, TRI, Reg.S) << "\n"); in processPredicateGPR()
231 LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n'); in processPredicateGPR()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCRegisterInfo.cpp68 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) in replaceFrameIndex()
69 << " for FrameReg=" << printReg(FrameReg, TRI) in replaceFrameIndex()

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