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Searched refs:isBuildVectorAllZeros (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h413 bool isBuildVectorAllZeros(const MachineInstr &MI,
H A DInstructionSelectorImpl.h358 if (!isBuildVectorAllZeros(*MI, MRI)) { in executeMatchTable()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp1113 bool llvm::isBuildVectorAllZeros(const MachineInstr &MI, in isBuildVectorAllZeros() function in llvm
1222 return isBuildVectorAllZeros(MI, MRI); in isNullOrNullSplat()
H A DCombinerHelper.cpp3079 return isBuildVectorAllZeros(*VecMI, MRI); in matchPtrAddZero()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp6794 if (ISD::isBuildVectorAllZeros(Vec.getNode())) { in insert1BitVector()
9909 if (ISD::isBuildVectorAllZeros(Op.getNode()) || in LowerBUILD_VECTORvXi1()
10710 if (ISD::isBuildVectorAllZeros(Op.getNode())) in materializeVectorConstant()
14828 if (ISD::isBuildVectorAllZeros(V1.getNode()) || in lowerShuffleAsPermuteAndUnpack()
14829 ISD::isBuildVectorAllZeros(V2.getNode())) in lowerShuffleAsPermuteAndUnpack()
47067 if (ISD::isBuildVectorAllZeros(N0.getNode())) in combineVectorShiftVar()
47121 if (ISD::isBuildVectorAllZeros(N0.getNode())) in combineVectorShiftImm()
51263 if (ISD::isBuildVectorAllZeros(N0.getNode())) in combineAndnp()
51267 if (ISD::isBuildVectorAllZeros(N1.getNode())) in combineAndnp()
54656 if (ISD::isBuildVectorAllZeros(RHS.getNode())) in combinePMULDQ()
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H A DX86ISelDAGToDAG.cpp762 ISD::isBuildVectorAllZeros(Root->getOperand(0).getNode()))) in IsProfitableToFold()
4539 if (ISD::isBuildVectorAllZeros(SetccOp0.getNode())) in tryVPTESTM()
4543 if (!ISD::isBuildVectorAllZeros(SetccOp1.getNode())) in tryVPTESTM()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h111 bool isBuildVectorAllZeros(const SDNode *N);
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp6987 bool ZeroN00 = ISD::isBuildVectorAllZeros(N0.getOperand(0).getNode()); in visitOR()
6988 bool ZeroN01 = ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode()); in visitOR()
6989 bool ZeroN10 = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode()); in visitOR()
6990 bool ZeroN11 = ISD::isBuildVectorAllZeros(N1.getOperand(1).getNode()); in visitOR()
10868 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode()); in visitVSELECT()
10873 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode()); in visitVSELECT()
10876 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode()); in visitVSELECT()
22020 if (N0AnyConst && !N1AnyConst && !ISD::isBuildVectorAllZeros(N0.getNode())) in combineShuffleOfScalars()
22022 if (!N0AnyConst && N1AnyConst && !ISD::isBuildVectorAllZeros(N1.getNode())) in combineShuffleOfScalars()
H A DTargetLowering.cpp807 (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode()))) in SimplifyMultipleUseDemandedBits()
1678 (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode()))) in SimplifyDemandedBits()
H A DSelectionDAG.cpp264 bool ISD::isBuildVectorAllZeros(const SDNode *N) { in isBuildVectorAllZeros() function in ISD
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6807 if (ISD::isBuildVectorAllZeros(Op1.getNode())) in LowerVSETCC()
6809 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) in LowerVSETCC()
6833 if (ISD::isBuildVectorAllZeros(Op1.getNode())) in LowerVSETCC()
6835 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) { in LowerVSETCC()
10099 return (ISD::isBuildVectorAllZeros(N.getNode()) || in isZeroVector()
16900 !ISD::isBuildVectorAllZeros(N0->getOperand(2).getNode())) in PerformVECREDUCE_ADDCombine()
16952 !ISD::isBuildVectorAllZeros(N0->getOperand(2).getNode())) in PerformVECREDUCE_ADDCombine()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4792 return ISD::isBuildVectorAllZeros(N.getNode()); in isZeroVector()
6277 if (ISD::isBuildVectorAllZeros(Op0.getNode())) { in combineMERGE()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15553 ISD::isBuildVectorAllZeros(V1.getOperand(0).getNode()) && in PerformDAGCombine()
15559 ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()) && in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2082 if (ISD::isBuildVectorAllZeros(Op.getNode())) { in lowerBUILD_VECTOR()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp14703 if (!ISD::isBuildVectorAllZeros(Sub.getOperand(0).getNode())) in tryCombineToBSL()