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Searched refs:hasSubClassEq (Results 1 – 25 of 40) sorted by relevance

12

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp46 if (X86::GR8RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
47 X86::GR16RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
48 X86::GR32RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
49 X86::GR64RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
50 X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
51 X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC)) in getRegBankFromRegClass()
54 if (X86::FR32XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
55 X86::FR64XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
56 X86::VR128XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
57 X86::VR256XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
[all …]
H A DX86DomainReassignment.cpp46 return X86::GR64RegClass.hasSubClassEq(RC) || in isGPR()
47 X86::GR32RegClass.hasSubClassEq(RC) || in isGPR()
48 X86::GR16RegClass.hasSubClassEq(RC) || in isGPR()
49 X86::GR8RegClass.hasSubClassEq(RC); in isGPR()
54 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
70 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
72 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
74 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
76 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
H A DX86InstrInfo.cpp3359 if (X86::GR16RegClass.hasSubClassEq(RC) || in canInsertSelect()
3360 X86::GR32RegClass.hasSubClassEq(RC) || in canInsertSelect()
3361 X86::GR64RegClass.hasSubClassEq(RC)) { in canInsertSelect()
3585 if (X86::VK16RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3590 if (X86::GR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3592 if (X86::FR32XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3600 if (X86::RFP32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3620 if (X86::GR64RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3622 if (X86::FR64XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3630 if (X86::VR64RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp254 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
283 else if (Mips::LO32RegClass.hasSubClassEq(RC)) in storeRegToStack()
285 else if (Mips::LO64RegClass.hasSubClassEq(RC)) in storeRegToStack()
287 else if (Mips::HI32RegClass.hasSubClassEq(RC)) in storeRegToStack()
289 else if (Mips::HI64RegClass.hasSubClassEq(RC)) in storeRegToStack()
291 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) in storeRegToStack()
298 if (Mips::HI32RegClass.hasSubClassEq(RC)) { in storeRegToStack()
332 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
361 else if (Mips::HI32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
363 else if (Mips::HI64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
[all …]
H A DMips16InstrInfo.cpp116 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in storeRegToStack()
135 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in loadRegFromStack()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp63 if (LoongArch::GPRRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
67 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
69 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
96 if (LoongArch::GPRRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
100 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
102 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp469 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
482 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
496 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
498 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
500 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
502 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
504 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
506 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
508 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
510 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp406 if (CSKY::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
408 } else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
411 } else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
413 else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
415 else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
417 else if (v3df && CSKY::FPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
449 if (CSKY::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
451 } else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
456 else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
458 else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp625 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) || in canInsertSelect()
639 if (AArch64::FPR64RegClass.hasSubClassEq(RC) || in canInsertSelect()
640 AArch64::FPR32RegClass.hasSubClassEq(RC)) { in canInsertSelect()
3798 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
3802 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
3855 if (AArch64::DDDRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
3877 if (AArch64::QQQRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
3952 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
3956 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
4009 if (AArch64::DDDRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp421 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
424 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
459 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
462 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegisterBank.cpp48 if (!RC.hasSubClassEq(&SubRC)) in verify()
H A DMachineCombiner.cpp188 return SrcRC->hasSuperClassEq(DstRC) || SrcRC->hasSubClassEq(DstRC); in isTransientMI()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1559 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1560 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
1561 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1562 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
1593 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
1874 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1875 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
1946 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in StoreRegToStackSlot()
1947 PPC::CRBITRCRegClass.hasSubClassEq(RC)) in StoreRegToStackSlot()
2001 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in LoadRegFromStackSlot()
[all …]
H A DPPCVSXCopy.cpp54 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp704 if (M68k::DR8RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
706 if (M68k::CCRCRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
711 assert(M68k::XR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
714 assert(M68k::XR32RegClass.hasSubClassEq(RC) && "Unknown 4-byte regclass"); in getLoadStoreRegOpcode()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h123 return RC != this && hasSubClassEq(RC); in hasSubClass()
127 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() function
140 return RC->hasSubClassEq(this); in hasSuperClassEq()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp1127 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1138 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1163 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1243 if (ARM::QQPRRegClass.hasSubClassEq(RC) || in storeRegToStackSlot()
1244 ARM::MQQPRRegClass.hasSubClassEq(RC) || in storeRegToStackSlot()
1384 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1394 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1416 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1495 if (ARM::QQPRRegClass.hasSubClassEq(RC) || in loadRegFromStackSlot()
1496 ARM::MQQPRRegClass.hasSubClassEq(RC) || in loadRegFromStackSlot()
[all …]
H A DThumb2InstrInfo.cpp177 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
187 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
219 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
228 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp311 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
338 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp32 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in getRC32()
36 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) || in getRC32()
H A DSystemZInstrInfo.cpp558 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) || in canInsertSelect()
559 SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in canInsertSelect()
560 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { in canInsertSelect()
585 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) { in insertSelect()
600 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { in insertSelect()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp496 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
510 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
554 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
566 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp967 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
975 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
979 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
983 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
987 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
991 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1012 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1021 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1024 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1027 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp297 if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { in shouldCoalesce()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp59 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in storeRegToStackSlot()
79 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in loadRegFromStackSlot()

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