541   bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));  in canFoldIntoCSel()
625   if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||  in canInsertSelect()
626       AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in canInsertSelect()
639   if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||  in canInsertSelect()
640       AArch64::FPR32RegClass.hasSubClassEq(RC)) {  in canInsertSelect()
1199     } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&  in UpdateOperandRegClass()
3798     if (AArch64::FPR8RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
3802     if (AArch64::FPR16RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
3804     else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3811     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3817     } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
3821     if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3827     } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3829     } else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3837     if (AArch64::FPR128RegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
3839     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3843     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3848     } else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3855     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3862     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3866     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3870     } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3877     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3881     } else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3888     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3892     } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
3952     if (AArch64::FPR8RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
3956     if (AArch64::FPR16RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
3958     else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3965     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3971     } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
3975     if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3981     } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3983     } else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3991     if (AArch64::FPR128RegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
3993     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
3997     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
4002     } else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
4009     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
4016     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
4020     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
4024     } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
4031     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
4035     } else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
4042     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
4046     } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()