Lines Matching refs:hasSubClassEq

967   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
971   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
975   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
979   } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
983   } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
987   } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
991   } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1012   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1015   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1018   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1021   } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1024   } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1027   } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1030   } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()