1127       if (ARM::HPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1138       if (ARM::GPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1145       } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1152       } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1163       if (ARM::DPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1170       } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1191       if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {  in storeRegToStackSlot()
1207       } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&  in storeRegToStackSlot()
1219       if (ARM::DTripleRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1243       if (ARM::QQPRRegClass.hasSubClassEq(RC) ||  in storeRegToStackSlot()
1244           ARM::MQQPRRegClass.hasSubClassEq(RC) ||  in storeRegToStackSlot()
1245           ARM::DQuadRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1276       if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) &&  in storeRegToStackSlot()
1282       } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {  in storeRegToStackSlot()
1384     if (ARM::HPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1394     if (ARM::GPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1400     } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1406     } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1416     if (ARM::DPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1422     } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1448     if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {  in loadRegFromStackSlot()
1461     } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&  in loadRegFromStackSlot()
1472     if (ARM::DTripleRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1495      if (ARM::QQPRRegClass.hasSubClassEq(RC) ||  in loadRegFromStackSlot()
1496          ARM::MQQPRRegClass.hasSubClassEq(RC) ||  in loadRegFromStackSlot()
1497          ARM::DQuadRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()
1525     if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) &&  in loadRegFromStackSlot()
1530     } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {  in loadRegFromStackSlot()