Lines Matching refs:hasSubClassEq
469 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
473 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
476 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
479 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
482 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
485 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
488 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
491 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
494 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
496 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
498 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
500 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
502 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
504 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
506 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
508 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
510 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
512 else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
514 else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
563 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
567 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
570 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
573 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
576 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
579 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
582 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
585 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
588 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
590 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
592 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
594 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
596 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
598 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
600 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
602 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
604 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
606 else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
608 else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()