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Searched refs:getOpcode (Results 1 – 25 of 1054) sorted by relevance

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/llvm-project-15.0.7/bolt/lib/Target/AArch64/
H A DAArch64MCPlusBuilder.cpp59 return Inst.getOpcode() == AArch64::ADRP; in isADRP()
63 return Inst.getOpcode() == AArch64::ADR; in isADR()
79 Inst.getOpcode() == AArch64::TBZX); in isTB()
86 Inst.getOpcode() == AArch64::CBZX); in isCB()
194 if (Inst.getOpcode() != AArch64::ORRXrs) in isRegToRegMove()
206 return Inst.getOpcode() == AArch64::BLR; in isIndirectCall()
240 if (Inst.getOpcode() == AArch64::ADR) { in evaluateADR()
285 if (Inst.getOpcode() == AArch64::ADRP) in evaluateMemOperandTarget()
790 return Inst.getOpcode(); in getCondCode()
823 switch (Inst.getOpcode()) { in getPCRelEncodingSize()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DGenericMachineInstrs.h35 return isPreISelGenericOpcode(MI->getOpcode()); in classof()
66 switch (MI->getOpcode()) { in classof()
85 switch (MI->getOpcode()) { in classof()
100 return MI->getOpcode() == TargetOpcode::G_LOAD; in classof()
136 return MI->getOpcode() == TargetOpcode::G_STORE; in classof()
164 switch (MI->getOpcode()) { in classof()
226 return MI->getOpcode() == TargetOpcode::G_SELECT; in classof()
240 return MI->getOpcode() == TargetOpcode::G_ICMP || in classof()
241 MI->getOpcode() == TargetOpcode::G_FCMP; in classof()
249 return MI->getOpcode() == TargetOpcode::G_ICMP; in classof()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64MacroFusion.cpp38 switch (FirstMI->getOpcode()) { in isArithmeticBccPair()
82 switch (FirstMI->getOpcode()) { in isArithmeticCbzPair()
123 switch (SecondMI.getOpcode()) { in isAESPair()
147 switch (FirstMI->getOpcode()) { in isCryptoEORPair()
199 switch (SecondMI.getOpcode()) { in isAddressLdStPair()
227 switch (FirstMI->getOpcode()) { in isAddressLdStPair()
248 switch (FirstMI->getOpcode()) { in isCCSelectPair()
266 switch (FirstMI->getOpcode()) { in isCCSelectPair()
287 switch (SecondMI.getOpcode()) { in isArithmeticLogicPair()
327 switch (FirstMI->getOpcode()) { in isArithmeticLogicPair()
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/llvm-project-15.0.7/llvm/unittests/Transforms/Utils/
H A DIntegerDivisionTest.cpp41 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SDiv); in TEST()
46 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr); in TEST()
71 EXPECT_TRUE(BB->front().getOpcode() == Instruction::UDiv); in TEST()
76 EXPECT_TRUE(BB->front().getOpcode() == Instruction::ICmp); in TEST()
101 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem); in TEST()
106 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr); in TEST()
131 EXPECT_TRUE(BB->front().getOpcode() == Instruction::URem); in TEST()
136 EXPECT_TRUE(BB->front().getOpcode() == Instruction::ICmp); in TEST()
162 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SDiv); in TEST()
167 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr); in TEST()
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/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFMIChecking.cpp158 if (MI.getOpcode() != BPF::XADDW && in processAtomicInsts()
159 MI.getOpcode() != BPF::XADDD && in processAtomicInsts()
160 MI.getOpcode() != BPF::XADDW32) in processAtomicInsts()
189 if (MI.getOpcode() != BPF::XFADDW32 && MI.getOpcode() != BPF::XFADDD && in processAtomicInsts()
190 MI.getOpcode() != BPF::XFANDW32 && MI.getOpcode() != BPF::XFANDD && in processAtomicInsts()
191 MI.getOpcode() != BPF::XFXORW32 && MI.getOpcode() != BPF::XFXORD && in processAtomicInsts()
192 MI.getOpcode() != BPF::XFORW32 && MI.getOpcode() != BPF::XFORD) in processAtomicInsts()
200 switch (MI.getOpcode()) { in processAtomicInsts()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp162 if (Addr.getOpcode() == ISD::FrameIndex) in selectADDRrri()
164 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in selectADDRrri()
165 Addr.getOpcode() == ISD::TargetGlobalAddress || in selectADDRrri()
166 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in selectADDRrri()
227 Addr.getOpcode() == ISD::TargetGlobalAddress || in selectADDRzii()
258 Addr.getOpcode() == ISD::TargetGlobalAddress || in selectADDRzi()
281 if (Addr.getOpcode() == ISD::ADD) { in matchADDRrr()
283 } else if (Addr.getOpcode() == ISD::OR) { in matchADDRrr()
292 if (Addr.getOperand(0).getOpcode() == VEISD::Lo || in matchADDRrr()
293 Addr.getOperand(1).getOpcode() == VEISD::Lo) in matchADDRrr()
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/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVInstrInfo.cpp29 switch (MI.getOpcode()) { in isConstantInstr()
55 return MI.getOpcode() == SPIRV::OpTypeForwardPointer; in isTypeDeclInstr()
60 switch (MI.getOpcode()) { in isDecorationInstr()
73 switch (MI.getOpcode()) { in isHeaderInstr()
133 if (MI->getOpcode() == SPIRV::OpBranch) { in analyzeBranch()
136 } else if (MI->getOpcode() == SPIRV::OpBranchConditional) { in analyzeBranch()
198 if (MI.getOpcode() == SPIRV::GET_ID || MI.getOpcode() == SPIRV::GET_fID || in expandPostRAPseudo()
199 MI.getOpcode() == SPIRV::GET_pID || MI.getOpcode() == SPIRV::GET_vfID || in expandPostRAPseudo()
200 MI.getOpcode() == SPIRV::GET_vID) { in expandPostRAPseudo()
H A DSPIRVPreLegalizer.cpp155 switch (MI->getOpcode()) { in propagateSPIRVType()
259 if (MI.getOpcode() == TargetOpcode::G_CONSTANT) in generateAssignInstrs()
280 } else if (MI.getOpcode() == TargetOpcode::G_TRUNC || in generateAssignInstrs()
282 MI.getOpcode() == TargetOpcode::COPY || in generateAssignInstrs()
303 bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat; in createNewIdReg()
305 SpvType->getOpcode() == SPIRV::OpTypeVector && in createNewIdReg()
327 unsigned Opc = MI.getOpcode(); in processInstr()
355 if (isTypeFoldingSupported(MI.getOpcode())) in processInstrsWithTypeFolding()
364 if (MI.getOpcode() != SPIRV::ASSIGN_TYPE) in processInstrsWithTypeFolding()
433 assert(CBr->getOpcode() == SPIRV::G_BRCOND && in processSwitches()
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h201 inline unsigned getOpcode() const;
1123 return Node->getOpcode();
1368 switch (getOpcode()) {
1387 switch (N->getOpcode()) {
1444 unsigned Op = getOpcode();
2319 N->getOpcode() == ISD::STORE;
2347 return N->getOpcode() == ISD::LOAD;
2416 switch (getOpcode()) {
2429 switch (getOpcode()) {
2457 N->getOpcode() == ISD::VP_LOAD || N->getOpcode() == ISD::VP_STORE;
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600EmitClauseMarkers.cpp38 switch (MI.getOpcode()) { in OccupiedDwords()
52 if (TII->isLDSRetInstr(MI.getOpcode())) in OccupiedDwords()
56 TII->isReductionOp(MI.getOpcode())) in OccupiedDwords()
71 if (TII->isALUInstr(MI.getOpcode())) in isALU()
73 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode())) in isALU()
75 switch (MI.getOpcode()) { in isALU()
89 switch (MI.getOpcode()) { in IsTrivialInst()
119 if (!TII->isALUInstr(MI.getOpcode()) && MI.getOpcode() != R600::DOT_4) in SubstituteKCacheBank()
125 (TII->isALUInstr(MI.getOpcode()) || MI.getOpcode() == R600::DOT_4) && in SubstituteKCacheBank()
240 if (I->getOpcode() == R600::PRED_X) { in MakeALUClause()
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H A DR600Packetizer.cpp67 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) in getPreviousVector()
84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
93 if (BI->getOpcode() == R600::DOT4_r600 || in getPreviousVector()
94 BI->getOpcode() == R600::DOT4_eg) { in getPreviousVector()
131 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Op); in substitutePV()
166 if (!TII->isALUInstr(MI.getOpcode())) in isSoloInstruction()
168 if (MI.getOpcode() == R600::GROUP_BARRIER) in isSoloInstruction()
172 return TII->isLDSInstr(MI.getOpcode()); in isSoloInstruction()
297 unsigned Op = TII->getOperandIdx(MI->getOpcode(), in addToPacket()
302 TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle); in addToPacket()
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H A DR600InstrInfo.cpp139 if (isALUInstr(MI.getOpcode())) in canBeConsideredALU()
143 switch (MI.getOpcode()) { in canBeConsideredALU()
163 return isTransOnly(MI.getOpcode()); in isTransOnly()
171 return isVectorOnly(MI.getOpcode()); in isVectorOnly()
218 if (!isALUInstr(MI.getOpcode())) { in readsLDSSrcReg()
260 if (MI.getOpcode() == R600::DOT_4) { in getSrcs()
661 if (isBranch(I->getOpcode())) in analyzeBranch()
663 if (!isJump(I->getOpcode())) { in analyzeBranch()
789 switch (I->getOpcode()) { in removeBranch()
813 switch (I->getOpcode()) { in removeBranch()
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/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DOperator.h42 unsigned getOpcode() const { in getOpcode() function
44 return I->getOpcode(); in getOpcode()
45 return cast<ConstantExpr>(this)->getOpcode(); in getOpcode()
50 static unsigned getOpcode(const Value *V) { in getOpcode() function
52 return I->getOpcode(); in getOpcode()
54 return CE->getOpcode(); in getOpcode()
110 I->getOpcode() == Instruction::Shl; in classof()
297 Opcode = I->getOpcode(); in classof()
299 Opcode = CE->getOpcode(); in classof()
336 return I->getOpcode() == Opc; in classof()
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/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelDAGToDAG.cpp113 if (Addr.getOpcode() == ISD::OR && in selectAddrSls()
114 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL) { in selectAddrSls()
163 if ((Addr.getOpcode() == ISD::TargetExternalSymbol || in selectAddrRiSpls()
164 Addr.getOpcode() == ISD::TargetGlobalAddress)) in selectAddrRiSpls()
192 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL) in selectAddrRiSpls()
214 if (Addr.getOpcode() == ISD::FrameIndex) in selectAddrRr()
218 if ((Addr.getOpcode() == ISD::TargetExternalSymbol || in selectAddrRr()
219 Addr.getOpcode() == ISD::TargetGlobalAddress)) in selectAddrRr()
232 if (Addr.getOperand(0).getOpcode() == LanaiISD::HI || in selectAddrRr()
233 Addr.getOperand(0).getOpcode() == LanaiISD::LO || in selectAddrRr()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp94 if (HiLUI.getOpcode() != RISCV::LUI || in INITIALIZE_PASS()
102 if (LoADDI->getOpcode() != RISCV::ADDI || in INITIALIZE_PASS()
159 if (OffsetTail.getOpcode() == RISCV::ADDI || in matchLargeOffset()
160 OffsetTail.getOpcode() == RISCV::ADDIW) { in matchLargeOffset()
170 if (OffsetLui.getOpcode() != RISCV::LUI || in matchLargeOffset()
187 } else if (OffsetTail.getOpcode() == RISCV::LUI) { in matchLargeOffset()
226 if (OffsetTail.getOpcode() != RISCV::ADDI) in matchShiftedOffset()
237 switch (TailShXAdd.getOpcode()) { in matchShiftedOffset()
261 switch (Tail.getOpcode()) { in detectAndFoldOffset()
274 if (TailTail.getOpcode() == RISCV::ADDI) { in detectAndFoldOffset()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp136 if (II->getOpcode() == TargetOpcode::KILL) in INITIALIZE_PASS_DEPENDENCY()
220 if (MII->getOpcode() == TargetOpcode::KILL || in commonChecksToProhibitNewValueJump()
221 MII->getOpcode() == TargetOpcode::PHI || in commonChecksToProhibitNewValueJump()
222 MII->getOpcode() == TargetOpcode::COPY) in commonChecksToProhibitNewValueJump()
229 if (MII->getOpcode() == Hexagon::LDriw_pred || in commonChecksToProhibitNewValueJump()
230 MII->getOpcode() == Hexagon::STriw_pred) in commonChecksToProhibitNewValueJump()
257 switch (MI.getOpcode()) { in canCompareBeNewValueJump()
295 if (def->getOpcode() == TargetOpcode::COPY) in canCompareBeNewValueJump()
347 switch (MI->getOpcode()) { in getNewValueJumpOpcode()
429 switch (MI.getOpcode()) { in isNewValueJumpCandidate()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp128 if (T.getOpcode() == ARM::t2LoopEndDec && in findLoopComponents()
149 if (LoopEnd->getOpcode() == ARM::t2LoopEndDec) in findLoopComponents()
189 assert(MI->getOpcode() == ARM::t2WhileLoopSetup && in RevertWhileLoopSetup()
204 if (I.getOpcode() == ARM::t2WhileLoopStart) { in RevertWhileLoopSetup()
241 return MI.getOpcode() == ARM::t2WhileLoopStart; in LowerWhileLoopStart()
471 if (VCTP->getOpcode() != FirstVCTP->getOpcode() || in ConvertTailPredLoop()
582 assert(IsVCMP(Cond.getOpcode()) && IsVCMP(Prev.getOpcode())); in IsVPNOTEquivalent()
585 if (Cond.getOpcode() != Prev.getOpcode()) in IsVPNOTEquivalent()
599 if (!CanHaveSwappedOperands(Cond.getOpcode())) in IsVPNOTEquivalent()
871 if (!IsVCMP(Instr.getOpcode())) { in ReplaceVCMPsByVPNOTs()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp177 unsigned Opcode = MI->getOpcode(); in getKnownLeadingZeroCount()
442 switch (MI.getOpcode()) { in simplifyCode()
948 (LiMI->getOpcode() != PPC::LI && LiMI->getOpcode() != PPC::LI8) in simplifyCode()
982 if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8) in simplifyCode()
1385 is64bitCmpOp(CMPI1->getOpcode()) != is64bitCmpOp(CMPI2->getOpcode())) in eliminateRedundantCompare()
1393 if (CMPI1->getOpcode() != CMPI2->getOpcode()) { in eliminateRedundantCompare()
1410 CMPI1->getOpcode() == getSignedCmpOpCode(CMPI2->getOpcode())) in eliminateRedundantCompare()
1411 NewOpCode = CMPI1->getOpcode(); in eliminateRedundantCompare()
1413 getSignedCmpOpCode(CMPI1->getOpcode()) == CMPI2->getOpcode()) in eliminateRedundantCompare()
1595 if (MI.getOpcode() != PPC::RLDICR) in emitRLDICWhenLoweringJumpTables()
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H A DPPCBranchSelector.cpp142 if (TII->isPrefixed(MI.getOpcode())) { in ComputeBlockSizes()
331 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) && in runOnMachineFunction()
334 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ || in runOnMachineFunction()
335 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) && in runOnMachineFunction()
358 if (I->getOpcode() == PPC::BCC) { in runOnMachineFunction()
369 } else if (I->getOpcode() == PPC::BC) { in runOnMachineFunction()
372 } else if (I->getOpcode() == PPC::BCn) { in runOnMachineFunction()
375 } else if (I->getOpcode() == PPC::BDNZ) { in runOnMachineFunction()
377 } else if (I->getOpcode() == PPC::BDNZ8) { in runOnMachineFunction()
379 } else if (I->getOpcode() == PPC::BDZ) { in runOnMachineFunction()
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/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelDAGToDAG.cpp77 if (Addr.getOpcode() == ARCISD::GAWRAPPER) { in SelectAddrModeImm()
87 if (Addr.getOpcode() == ARCISD::GAWRAPPER) { in SelectAddrModeS9()
91 if (Addr.getOpcode() != ISD::ADD && Addr.getOpcode() != ISD::SUB && in SelectAddrModeS9()
93 if (Addr.getOpcode() == ISD::FrameIndex) { in SelectAddrModeS9()
107 if (Addr.getOpcode() == ISD::SUB) in SelectAddrModeS9()
114 if (Base.getOpcode() == ISD::FrameIndex) { in SelectAddrModeS9()
131 if (Addr.getOpcode() == ARCISD::GAWRAPPER) { in SelectAddrModeFar()
136 if (Addr.getOpcode() == ISD::SUB) in SelectAddrModeFar()
154 if (Addr.getOpcode() == ISD::ADD) { in SelectFrameADDR_ri()
170 switch (N->getOpcode()) { in Select()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyCFGStackify.cpp305 if (MI.getOpcode() == WebAssembly::LOOP) { in placeBlockMarker()
320 MI.getOpcode() == WebAssembly::TRY) { in placeBlockMarker()
367 if (MI.getOpcode() == WebAssembly::LOOP || in placeBlockMarker()
368 MI.getOpcode() == WebAssembly::TRY) in placeBlockMarker()
542 MI.getOpcode() == WebAssembly::TRY) in placeTryMarker()
616 MI.getOpcode() == WebAssembly::BLOCK) in placeTryMarker()
757 if (MI.getOpcode() != WebAssembly::TRY) in removeUnnecessaryInstrs()
827 if (!WebAssembly::isTee(MI.getOpcode())) in unstackifyVRegsUsedInSplitBB()
1447 switch (MI.getOpcode()) { in recalculateScopeTops()
1493 switch (MI.getOpcode()) { in fixEndsAtEndOfFunction()
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/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp116 (MI->getOpcode() == SP::RESTORErr in runOnMachineBasicBlock()
125 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD in runOnMachineBasicBlock()
126 || MI->getOpcode() == SP::FCMPQ)) { in runOnMachineBasicBlock()
177 unsigned Opc = slot->getOpcode(); in findDelayInstr()
186 if (J->getOpcode() == SP::RESTORErr in findDelayInstr()
272 unsigned Opcode = candidate->getOpcode(); in delayHasHazard()
298 switch(MI->getOpcode()) { in insertCallDefsUses()
360 switch (I->getOpcode()) { in needsUnimp()
419 if (OrMI->getOpcode() == SP::ORrr in combineRestoreOR()
424 if (OrMI->getOpcode() == SP::ORri in combineRestoreOR()
[all …]
H A DSparcISelDAGToDAG.cpp83 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDRri()
84 Addr.getOpcode() == ISD::TargetGlobalAddress || in SelectADDRri()
85 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in SelectADDRri()
88 if (Addr.getOpcode() == ISD::ADD) { in SelectADDRri()
104 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { in SelectADDRri()
109 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { in SelectADDRri()
123 Addr.getOpcode() == ISD::TargetGlobalAddress || in SelectADDRrr()
127 if (Addr.getOpcode() == ISD::ADD) { in SelectADDRrr()
132 Addr.getOperand(1).getOpcode() == SPISD::Lo) in SelectADDRrr()
328 switch (N->getOpcode()) { in Select()
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/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h41 return Info->get(Inst.getOpcode()).isBranch(); in isBranch()
45 return Info->get(Inst.getOpcode()).isConditionalBranch(); in isConditionalBranch()
49 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); in isUnconditionalBranch()
53 return Info->get(Inst.getOpcode()).isIndirectBranch(); in isIndirectBranch()
57 return Info->get(Inst.getOpcode()).isCall(); in isCall()
61 return Info->get(Inst.getOpcode()).isReturn(); in isReturn()
65 return Info->get(Inst.getOpcode()).isTerminator(); in isTerminator()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp6074 if (N0.getOpcode() != ISD::XOR && N0.getOpcode() != ISD::ADD) in foldAndToUsubsat()
6416 if (N0.getOpcode() == N1.getOpcode()) in visitAND()
6560 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
6562 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) in MatchBSwapHWordLow()
7094 if (N0.getOpcode() == N1.getOpcode()) in visitOR()
7211 if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() || in extractShiftForRotate()
7566 if (LHSShift.getOpcode() == RHSShift.getOpcode()) in MatchRotate()
9182 if (LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH()
10968 if (OpRHS.getOpcode() == CondRHS.getOpcode() && in visitVSELECT()
23524 if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode() && in scalarizeBinOpOfSplats()
[all …]

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