Lines Matching refs:getOpcode
261 assert(N->getOpcode() != ISD::DELETED_NODE && in AddToWorklist()
266 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
654 switch (StoreVal.getOpcode()) { in getStoreSource()
897 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
905 (N.getOpcode() == ISD::STRICT_FSETCC || in isSetCCEquivalent()
906 N.getOpcode() == ISD::STRICT_FSETCCS)) { in isSetCCEquivalent()
913 if (N.getOpcode() != ISD::SELECT_CC || !TLI.isConstTrueVal(N.getOperand(2)) || in isSetCCEquivalent()
970 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) in isConstantOrConstantVector()
987 if (V.getOpcode() != ISD::BUILD_VECTOR) in isAnyConstantBuildVector()
996 (LD->getOperand(2).getOpcode() != ISD::TargetConstant || in canSplitIdx()
1014 if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD) in reassociationCanBreakAddressingModePattern()
1057 if (GA->getOpcode() == ISD::GlobalAddress && TLI.isOffsetFoldingLegal(GA)) in reassociationCanBreakAddressingModePattern()
1088 if (N0.getOpcode() != Opc) in reassociateOpsCommutative()
1287 unsigned Opc = Op.getOpcode(); in PromoteOperand()
1354 unsigned Opc = Op.getOpcode(); in PromoteIntBinOp()
1422 unsigned Opc = Op.getOpcode(); in PromoteIntShiftOp()
1455 if (Op && Op.getOpcode() != ISD::DELETED_NODE) in PromoteIntShiftOp()
1471 unsigned Opc = Op.getOpcode(); in PromoteExtend()
1484 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0)); in PromoteExtend()
1502 unsigned Opc = Op.getOpcode(); in PromoteLoad()
1634 assert(N->getOpcode() != ISD::DELETED_NODE && in Run()
1635 RV.getOpcode() != ISD::DELETED_NODE && in Run()
1653 if (RV.getOpcode() != ISD::EntryToken) { in Run()
1671 switch (N->getOpcode()) { in visit()
1826 assert(N->getOpcode() != ISD::DELETED_NODE && in combine()
1829 if (N->getOpcode() >= ISD::BUILTIN_OP_END || in combine()
1830 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { in combine()
1842 switch (N->getOpcode()) { in combine()
1871 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode())) { in combine()
1878 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops, in combine()
1924 if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor) in visitTokenFactor()
1953 switch (Op.getOpcode()) { in visitTokenFactor()
2039 switch (CurNode->getOpcode()) { in visitTokenFactor()
2150 if (N->getOpcode() == ISD::ADD) { in canFoldInAddressingMode()
2159 } else if (N->getOpcode() == ISD::SUB) { in canFoldInAddressingMode()
2190 if (!N1.hasOneUse() || N1.getOpcode() != ISD::VSELECT) in foldSelectWithIdentityConstant()
2193 unsigned Opcode = N->getOpcode(); in foldSelectWithIdentityConstant()
2247 assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && in foldBinOpIntoSelect()
2251 auto BinOpcode = BO->getOpcode(); in foldBinOpIntoSelect()
2257 if (TLI.isCommutativeBinOp(BO->getOpcode())) in foldBinOpIntoSelect()
2267 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) { in foldBinOpIntoSelect()
2272 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) in foldBinOpIntoSelect()
2325 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && in foldAddSubBoolOfMaskedVal()
2331 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubBoolOfMaskedVal()
2335 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND) in foldAddSubBoolOfMaskedVal()
2339 if (Z.getOperand(0).getOpcode() != ISD::SETCC || in foldAddSubBoolOfMaskedVal()
2347 SetCC.getOperand(0).getOpcode() != ISD::AND || in foldAddSubBoolOfMaskedVal()
2366 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && in foldAddSubOfSignBit()
2371 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubOfSignBit()
2375 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2406 unsigned Opcode = V.getOpcode(); in isADDLike()
2452 if (N0.getOpcode() == ISD::SUB) { in visitADDLike()
2469 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() && in visitADDLike()
2518 if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0))) in visitADDLike()
2522 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) in visitADDLike()
2526 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) in visitADDLike()
2530 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) in visitADDLike()
2534 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && in visitADDLike()
2540 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && in visitADDLike()
2546 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && in visitADDLike()
2552 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && in visitADDLike()
2558 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && in visitADDLike()
2559 N1.getOperand(0).getOpcode() == ISD::SUB && in visitADDLike()
2561 return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0), in visitADDLike()
2565 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && in visitADDLike()
2579 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) { in visitADDLike()
2600 if (N0.getOpcode() == ISD::ADD) { in visitADDLike()
2619 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD && in visitADDLike()
2628 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitADDLike()
2664 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { in visitADD()
2671 if ((N0.getOpcode() == ISD::ADD) && in visitADD()
2672 (N0.getOperand(1).getOpcode() == ISD::VSCALE) && in visitADD()
2673 (N1.getOpcode() == ISD::VSCALE)) { in visitADD()
2681 if (N0.getOpcode() == ISD::STEP_VECTOR && in visitADD()
2682 N1.getOpcode() == ISD::STEP_VECTOR) { in visitADD()
2690 if ((N0.getOpcode() == ISD::ADD) && in visitADD()
2691 (N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR) && in visitADD()
2692 (N1.getOpcode() == ISD::STEP_VECTOR)) { in visitADD()
2704 unsigned Opcode = N->getOpcode(); in visitADDSAT()
2750 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) { in getAsCarry()
2755 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) { in getAsCarry()
2768 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY && in getAsCarry()
2769 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO) in getAsCarry()
2773 if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT)) in getAsCarry()
2792 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1))) in foldAddSubMasked1()
2811 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB && in visitADDLikeCommutative()
2825 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD && in visitADDLikeCommutative()
2832 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse()) { in visitADDLikeCommutative()
2851 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADDLikeCommutative()
2859 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitADDLikeCommutative()
2869 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) && in visitADDLikeCommutative()
2927 if (V.getOpcode() != ISD::XOR) in extractBooleanFlip()
2960 bool IsSigned = (ISD::SADDO == N->getOpcode()); in visitADDO()
2973 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); in visitADDO()
3010 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) { in visitUADDOLike()
3040 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitADDE()
3134 if (Carry1.getOpcode() != ISD::UADDO) in combineADDCARRYDiamond()
3143 if (Carry0.getOpcode() == ISD::ADDCARRY && in combineADDCARRYDiamond()
3146 } else if (Carry0.getOpcode() == ISD::UADDO && in combineADDCARRYDiamond()
3229 unsigned Opcode = Carry0.getOpcode(); in combineCarryDiamond()
3230 if (Opcode != Carry1.getOpcode()) in combineCarryDiamond()
3258 if (CarryIn.getOpcode() != ISD::ZERO_EXTEND) in combineCarryDiamond()
3283 if (N->getOpcode() == ISD::AND) in combineCarryDiamond()
3304 if ((N0.getOpcode() == ISD::ADD || in visitADDCARRYLike()
3305 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 && in visitADDCARRYLike()
3358 if (N->getOpcode() != ISD::SUB || in foldSubToUSubSat()
3368 if (Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) { in foldSubToUSubSat()
3377 if (Op1.getOpcode() == ISD::UMIN && Op1.hasOneUse()) { in foldSubToUSubSat()
3387 if (Op1.getOpcode() == ISD::TRUNCATE && in foldSubToUSubSat()
3388 Op1.getOperand(0).getOpcode() == ISD::UMIN && in foldSubToUSubSat()
3392 if (MinLHS.getOpcode() == ISD::ZERO_EXTEND && MinLHS.getOperand(0) == Op0) in foldSubToUSubSat()
3395 if (MinRHS.getOpcode() == ISD::ZERO_EXTEND && MinRHS.getOperand(0) == Op0) in foldSubToUSubSat()
3421 if (N->getOpcode() == ISD::FREEZE && N.hasOneUse()) in visitSUB()
3462 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
3465 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
3486 if (N1.getOpcode() == ISD::ABS && N1.hasOneUse() && in visitSUB()
3494 if (N1S && N1S.getOpcode() == ISD::SUB && in visitSUB()
3508 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) in visitSUB()
3512 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) in visitSUB()
3516 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) in visitSUB()
3520 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) in visitSUB()
3524 if (N0.getOpcode() == ISD::ADD) { in visitSUB()
3531 if (N1.getOpcode() == ISD::ADD) { in visitSUB()
3538 if (N0.getOpcode() == ISD::SUB) { in visitSUB()
3545 if (N0.getOpcode() == ISD::SUB) { in visitSUB()
3552 if (N0.getOpcode() == ISD::ADD && in visitSUB()
3553 (N0.getOperand(1).getOpcode() == ISD::SUB || in visitSUB()
3554 N0.getOperand(1).getOpcode() == ISD::ADD) && in visitSUB()
3556 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0), in visitSUB()
3560 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD && in visitSUB()
3566 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB && in visitSUB()
3572 if (N1.getOpcode() == ISD::SUB && N1.hasOneUse()) in visitSUB()
3578 if (N1.getOpcode() == ISD::AND) { in visitSUB()
3592 if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) { in visitSUB()
3593 if (N1.getOperand(0).getOpcode() == ISD::SUB && in visitSUB()
3600 if (N1.getOperand(1).getOpcode() == ISD::SUB && in visitSUB()
3628 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && isOneOrOneSplat(N1)) { in visitSUB()
3645 if (N0.hasOneUse() && N0.getOpcode() == ISD::ADD && in visitSUB()
3651 if (N1.hasOneUse() && N1.getOpcode() == ISD::ADD && in visitSUB()
3658 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && in visitSUB()
3664 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && in visitSUB()
3673 if (N1.getOpcode() == ISD::ZERO_EXTEND && in visitSUB()
3683 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) { in visitSUB()
3697 if (N1C && GA->getOpcode() == ISD::GlobalAddress) in visitSUB()
3709 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitSUB()
3719 if (N1.getOpcode() == ISD::VSCALE) { in visitSUB()
3725 if (N1.getOpcode() == ISD::STEP_VECTOR && N1.hasOneUse()) { in visitSUB()
3733 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { in visitSUB()
3746 if (N1.getOpcode() == ISD::SHL) { in visitSUB()
3793 if (SDValue C = DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1})) in visitSUBSAT()
3845 bool IsSigned = (ISD::SSUBO == N->getOpcode()); in visitSUBO()
3886 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitSUBE()
3937 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale); in visitMULFIX()
4073 if (N0.getOpcode() == ISD::SHL) { in visitMUL()
4085 if (N0.getOpcode() == ISD::SHL && in visitMUL()
4088 } else if (N1.getOpcode() == ISD::SHL && in visitMUL()
4102 N0.getOpcode() == ISD::ADD && in visitMUL()
4111 if (N0.getOpcode() == ISD::VSCALE) in visitMUL()
4120 if (N0.getOpcode() == ISD::STEP_VECTOR) in visitMUL()
4145 assert(N1.getOpcode() == ISD::BUILD_VECTOR && "Unknown constant vector"); in visitMUL()
4192 unsigned Opcode = Node->getOpcode(); in useDivRem()
4226 if (User == Node || User->getOpcode() == ISD::DELETED_NODE || in useDivRem()
4232 unsigned UserOpc = User->getOpcode(); in useDivRem()
4262 unsigned Opc = N->getOpcode(); in simplifyDivRem()
4521 if (N1.getOpcode() == ISD::SHL) { in visitUDIVLike()
4559 unsigned Opcode = N->getOpcode(); in visitREM()
4603 if ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) && in visitREM()
4788 unsigned Opcode = N->getOpcode(); in visitAVG()
4859 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType()))) in SimplifyNodeWithTwoResults()
4869 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType()))) in SimplifyNodeWithTwoResults()
4968 bool IsSigned = (ISD::SMULO == N->getOpcode()); in visitMULO()
4991 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); in visitMULO()
5049 if (N0 != N2 && (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) in isSaturatingMinMax()
5070 switch (N0.getOpcode()) { in isSaturatingMinMax()
5075 N0CC = N0.getOpcode() == ISD::SMIN ? ISD::SETLT : ISD::SETGT; in isSaturatingMinMax()
5086 if (N0.getOperand(0).getOpcode() != ISD::SETCC) in isSaturatingMinMax()
5131 if (!Fp || Fp.getOpcode() != ISD::FP_TO_SINT) in PerformMinMaxFpToSatCombine()
5155 (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) || in PerformUMinFpToSatCombine()
5156 N0.getOpcode() != ISD::FP_TO_UINT || CC != ISD::SETULT) in PerformUMinFpToSatCombine()
5188 unsigned Opcode = N->getOpcode(); in visitIMINMAX()
5246 unsigned LogicOpcode = N->getOpcode(); in hoistLogicOpWithSameOpcodeHands()
5247 unsigned HandOpcode = N0.getOpcode(); in hoistLogicOpWithSameOpcodeHands()
5250 assert(HandOpcode == N1.getOpcode() && "Bad input!"); in hoistLogicOpWithSameOpcodeHands()
5566 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && in visitANDLike()
5601 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { in visitANDLike()
5788 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) && in SearchForAndLoads()
5797 switch(Op.getOpcode()) { in SearchForAndLoads()
5821 EVT VT = Op.getOpcode() == ISD::AssertZext ? in SearchForAndLoads()
5894 if (And.getOpcode() == ISD ::AND) in BackwardsPropagateMask()
5918 if (And.getOpcode() == ISD ::AND) in BackwardsPropagateMask()
5938 assert(N->getOpcode() == ISD::AND); in unfoldExtremeBitClearingToShifts()
5954 OuterShift = M->getOpcode(); in unfoldExtremeBitClearingToShifts()
5990 assert(And->getOpcode() == ISD::AND && "Expected an 'and' op"); in combineShiftAnd1ToBitTest()
6000 if (And0.getOpcode() == ISD::ANY_EXTEND && And0.hasOneUse()) in combineShiftAnd1ToBitTest()
6017 if (Src.getOpcode() == ISD::TRUNCATE && Src.hasOneUse()) in combineShiftAnd1ToBitTest()
6022 if (Src.getOpcode() != ISD::SRL || !Src.hasOneUse()) in combineShiftAnd1ToBitTest()
6070 if (N0.getOpcode() == ISD::SRA) in foldAndToUsubsat()
6074 if (N0.getOpcode() != ISD::XOR && N0.getOpcode() != ISD::ADD) in foldAndToUsubsat()
6077 if (N1.getOpcode() != ISD::SRA || !N0.hasOneUse() || !N1.hasOneUse() || in foldAndToUsubsat()
6101 unsigned LogicOpcode = N->getOpcode(); in foldLogicOfShifts()
6110 unsigned ShiftOpcode = ShiftOp.getOpcode(); in foldLogicOfShifts()
6111 if (LogicOp.getOpcode() != LogicOpcode || in foldLogicOfShifts()
6123 if (LogicOp.getOperand(0).getOpcode() == ShiftOpcode && in foldLogicOfShifts()
6127 } else if (LogicOp.getOperand(1).getOpcode() == ShiftOpcode && in foldLogicOfShifts()
6228 if (N0.getOpcode() == ISD::OR && in visitAND()
6232 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitAND()
6257 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitAND()
6259 N0.getOperand(0).getOpcode() == ISD::LOAD && in visitAND()
6261 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) { in visitAND()
6262 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? in visitAND()
6356 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && N1C && in visitAND()
6357 ISD::isExtOpcode(N0.getOperand(0).getOpcode())) { in visitAND()
6399 if (N1C && N0.getOpcode() == ISD::LOAD && !VT.isVector()) in visitAND()
6416 if (N0.getOpcode() == N1.getOpcode()) in visitAND()
6432 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) { in visitAND()
6435 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND && in visitAND()
6438 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND && in visitAND()
6474 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) { in visitAND()
6493 if (LHS->getOpcode() != ISD::SIGN_EXTEND) in visitAND()
6533 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) in MatchBSwapHWordLow()
6535 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
6537 if (N0.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
6550 if (N1.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
6560 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
6562 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) in MatchBSwapHWordLow()
6576 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
6587 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
6645 unsigned Opc = N.getOpcode(); in isBSwapHWordElement()
6650 unsigned Opc0 = N0.getOpcode(); in isBSwapHWordElement()
6727 if (N.getOpcode() == ISD::OR) in isBSwapHWordPair()
6731 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) { in isBSwapHWordPair()
6749 assert(N->getOpcode() == ISD::OR && VT == MVT::i32 && in matchBSwapHWordOrAndAnd()
6753 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND) in matchBSwapHWordOrAndAnd()
6767 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd()
6820 } else if (N0.getOpcode() == ISD::OR) { in MatchBSwapHWord()
6867 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND && in visitORLike()
6893 if (N0.getOpcode() == ISD::AND && in visitORLike()
6894 N1.getOpcode() == ISD::AND && in visitORLike()
6910 if (N0.getOpcode() == ISD::AND) { in visitORCommutative()
6930 if (V->getOpcode() == ISD::ZERO_EXTEND) in visitORCommutative()
6936 if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL && in visitORCommutative()
6942 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL && in visitORCommutative()
7078 if (N0.getOpcode() == ISD::AND && N0->hasOneUse() && in visitOR()
7094 if (N0.getOpcode() == N1.getOpcode()) in visitOR()
7119 if (Op.getOpcode() == ISD::AND && in stripConstantMask()
7131 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { in matchRotateHalf()
7166 if (OppShift.getOpcode() != ISD::SHL && OppShift.getOpcode() != ISD::SRL) in extractShiftForRotate()
7180 if (OppShift.getOpcode() == ISD::SRL && OppShiftCst && in extractShiftForRotate()
7181 ExtractFrom.getOpcode() == ISD::ADD && in extractShiftForRotate()
7197 IsMulOrDiv = ExtractFrom.getOpcode() == MulOrDivVariant; in extractShiftForRotate()
7198 if (!IsMulOrDiv && ExtractFrom.getOpcode() != NeededShift) in extractShiftForRotate()
7205 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) && in extractShiftForRotate()
7206 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV))) in extractShiftForRotate()
7211 if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() || in extractShiftForRotate()
7334 if (Neg.getOpcode() != ISD::SUB) in matchRotateSub()
7369 (NegOp1.getOpcode() == ISD::TRUNCATE && Pos == NegOp1.getOperand(0))) in matchRotateSub()
7381 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) { in matchRotateSub()
7454 if (Op.getOpcode() != BinOpc) in MatchFunnelPosNeg()
7481 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N0.getOperand(1) && in MatchFunnelPosNeg()
7520 if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE && in MatchRotate()
7566 if (LHSShift.getOpcode() == RHSShift.getOpcode()) in MatchRotate()
7570 if (RHSShift.getOpcode() == ISD::SHL) { in MatchRotate()
7577 if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL) in MatchRotate()
7623 if (!Or.hasOneUse() || Or.getOpcode() != ISD::OR) in MatchRotate()
7692 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
7693 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
7694 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
7695 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && in MatchRotate()
7696 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
7697 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
7698 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
7699 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { in MatchRotate()
7795 switch (Op.getOpcode()) { in calculateByteProvider()
7835 return Op.getOpcode() == ISD::ZERO_EXTEND in calculateByteProvider()
7897 switch (Value.getOpcode()) { in stripTruncAndExt()
7982 if (Trunc.getOpcode() != ISD::TRUNCATE) in mergeTruncStores()
7988 if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) && in mergeTruncStores()
8137 assert(N->getOpcode() == ISD::OR && in MatchLoadCombine()
8320 assert(N->getOpcode() == ISD::XOR); in unfoldMaskedMerge()
8332 if (And.getOpcode() != ISD::AND || !And.hasOneUse()) in unfoldMaskedMerge()
8335 if (Xor.getOpcode() != ISD::XOR || !Xor.hasOneUse()) in unfoldMaskedMerge()
8456 unsigned N0Opcode = N0.getOpcode(); in visitXOR()
8530 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB && in visitXOR()
8537 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD && in visitXOR()
8555 if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) { in visitXOR()
8594 if (N0Opcode == N1.getOpcode()) in visitXOR()
8627 unsigned LogicOpcode = LogicOp.getOpcode(); in combineShiftOfShiftedLogic()
8633 unsigned ShiftOpcode = Shift->getOpcode(); in combineShiftOfShiftedLogic()
8640 if (V.getOpcode() != ShiftOpcode || !V.hasOneUse()) in combineShiftOfShiftedLogic()
8713 switch (LHS.getOpcode()) { in visitShiftByConstant()
8721 if (N->getOpcode() != ISD::SHL) in visitShiftByConstant()
8735 bool IsShiftByConstant = (BinOpLHSVal.getOpcode() == ISD::SHL || in visitShiftByConstant()
8736 BinOpLHSVal.getOpcode() == ISD::SRA || in visitShiftByConstant()
8737 BinOpLHSVal.getOpcode() == ISD::SRL) && in visitShiftByConstant()
8739 bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg || in visitShiftByConstant()
8740 BinOpLHSVal.getOpcode() == ISD::SELECT; in visitShiftByConstant()
8751 SDValue NewRHS = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(1), in visitShiftByConstant()
8755 SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0), in visitShiftByConstant()
8757 return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS); in visitShiftByConstant()
8761 assert(N->getOpcode() == ISD::TRUNCATE); in distributeTruncateThroughAnd()
8762 assert(N->getOperand(0).getOpcode() == ISD::AND); in distributeTruncateThroughAnd()
8812 return DAG.getNode(N->getOpcode(), dl, VT, N0, Amt); in visitRotate()
8826 if (N1.getOpcode() == ISD::TRUNCATE && in visitRotate()
8827 N1.getOperand(0).getOpcode() == ISD::AND) { in visitRotate()
8829 return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1); in visitRotate()
8832 unsigned NextOp = N0.getOpcode(); in visitRotate()
8841 bool SameSide = (N->getOpcode() == NextOp); in visitRotate()
8853 return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0), in visitRotate()
8884 if (N0.getOpcode() == ISD::AND) { in visitSHL()
8889 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC && in visitSHL()
8908 if (N1.getOpcode() == ISD::TRUNCATE && in visitSHL()
8909 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSHL()
8918 if (N0.getOpcode() == ISD::SHL) { in visitSHL()
8948 if ((N0.getOpcode() == ISD::ZERO_EXTEND || in visitSHL()
8949 N0.getOpcode() == ISD::ANY_EXTEND || in visitSHL()
8950 N0.getOpcode() == ISD::SIGN_EXTEND) && in visitSHL()
8951 N0.getOperand(0).getOpcode() == ISD::SHL) { in visitSHL()
8982 SDValue Ext = DAG.getNode(N0.getOpcode(), DL, VT, N0Op0.getOperand(0)); in visitSHL()
8992 if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() && in visitSHL()
8993 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSHL()
9015 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) { in visitSHL()
9041 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Diff); in visitSHL()
9049 if (N0.getOpcode() == ISD::SRL && in visitSHL()
9077 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) && in visitSHL()
9089 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) && in visitSHL()
9098 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Shl0, Shl1); in visitSHL()
9102 if (N0.getOpcode() == ISD::MUL && N0->hasOneUse()) { in visitSHL()
9115 if (N0.getOpcode() == ISD::VSCALE) in visitSHL()
9124 if (N0.getOpcode() == ISD::STEP_VECTOR) in visitSHL()
9142 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && in combineShiftToMULH()
9155 if (ShiftOperand.getOpcode() != ISD::MUL) in combineShiftToMULH()
9162 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH()
9163 bool IsZeroExt = LeftOp.getOpcode() == ISD::ZERO_EXTEND; in combineShiftToMULH()
9182 if (LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH()
9217 return (N->getOpcode() == ISD::SRA ? DAG.getSExtOrTrunc(Result, DL, WideVT) in combineShiftToMULH()
9251 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { in visitSRA()
9270 if (N0.getOpcode() == ISD::SRA) { in visitSRA()
9288 if (N1.getOpcode() == ISD::BUILD_VECTOR) in visitSRA()
9290 else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in visitSRA()
9306 if (N0.getOpcode() == ISD::SHL && N1C) { in visitSRA()
9346 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB) && N1C && in visitSRA()
9348 bool IsAdd = N0.getOpcode() == ISD::ADD; in visitSRA()
9350 if (Shl.getOpcode() == ISD::SHL && Shl.getOperand(1) == N1 && in visitSRA()
9387 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRA()
9388 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSRA()
9397 if (N0.getOpcode() == ISD::TRUNCATE && in visitSRA()
9398 (N0.getOperand(0).getOpcode() == ISD::SRL || in visitSRA()
9399 N0.getOperand(0).getOpcode() == ISD::SRA) && in visitSRA()
9472 if (N0.getOpcode() == ISD::SRL) { in visitSRL()
9497 if (N1C && N0.getOpcode() == ISD::TRUNCATE && in visitSRL()
9498 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSRL()
9537 if (N0.getOpcode() == ISD::SHL && in visitSRL()
9574 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitSRL()
9600 if (N0.getOpcode() == ISD::SRA) in visitSRL()
9605 if (N1C && N0.getOpcode() == ISD::CTLZ && in visitSRL()
9642 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRL()
9643 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSRL()
9680 if (Use->getOpcode() == ISD::BRCOND) in visitSRL()
9682 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { in visitSRL()
9685 if (Use->getOpcode() == ISD::BRCOND) in visitSRL()
9703 bool IsFSHL = N->getOpcode() == ISD::FSHL; in visitFunnelShift()
9724 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0, N1, in visitFunnelShift()
9822 DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, {N0, N1})) in visitSHLSAT()
9829 if (N->getOpcode() == ISD::SSHLSAT && N1C && in visitSHLSAT()
9834 if (N->getOpcode() == ISD::USHLSAT && N1C && in visitSHLSAT()
9851 if (AbsOp1.getOpcode() != ISD::SUB) in combineABSToABD()
9857 unsigned Opc0 = Op0.getOpcode(); in combineABSToABD()
9859 if (Opc0 != Op1.getOpcode() || in combineABSToABD()
9894 if (N0.getOpcode() == ISD::ABS) in visitABS()
9915 if (N0.getOpcode() == ISD::BSWAP) in visitBSWAP()
9922 if (N0.getOpcode() == ISD::BITREVERSE && N0.hasOneUse()) { in visitBSWAP()
9930 if (BW >= 32 && N0.getOpcode() == ISD::SHL && N0.hasOneUse()) { in visitBSWAP()
9952 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitBSWAP()
9958 unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL; in visitBSWAP()
9974 if (N0.getOpcode() == ISD::BITREVERSE) in visitBITREVERSE()
10114 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() || in foldSelectOfConstantsUsingSra()
10251 assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT) && in foldBoolSelectToLogic()
10289 if (N0.getOpcode() != ISD::SETCC || !N0.hasOneUse()) in foldVSelectToSignBitSplatMask()
10377 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) { in visitSELECT()
10390 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) { in visitSELECT()
10404 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) { in visitSELECT()
10423 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) { in visitSELECT()
10450 if (N0.getOpcode() == ISD::SETCC) { in visitSELECT()
10470 N2.getOpcode() == ISD::ADD && Cond0 == N2.getOperand(0)) { in visitSELECT()
10524 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
10525 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
10526 Cond.getOpcode() == ISD::BUILD_VECTOR); in ConvertSelectToConcatVector()
10572 if (!isNullConstant(BasePtr) || Index.getOpcode() != ISD::ADD) in refineUniformBase()
10596 if (Index.getOpcode() == ISD::ZERO_EXTEND) { in refineIndexType()
10610 if (Index.getOpcode() == ISD::SIGN_EXTEND && in refineIndexType()
10694 if (N->getOpcode() != ISD::DELETED_NODE) in visitMSTORE()
10703 if ((Value.getOpcode() == ISD::TRUNCATE) && Value->hasOneUse() && in visitMSTORE()
10864 if (N0.getOpcode() == ISD::SETCC) { in visitVSELECT()
10872 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1)) in visitVSELECT()
10875 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1)) in visitVSELECT()
10921 if (LHS.getOpcode() == ISD::LOAD && LHS.hasOneUse() && in visitVSELECT()
10951 if (Other && Other.getOpcode() == ISD::ADD) { in visitVSELECT()
10968 if (OpRHS.getOpcode() == CondRHS.getOpcode() && in visitVSELECT()
10969 (OpRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
10970 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) && in visitVSELECT()
11002 if (Other && Other.getOpcode() == ISD::TRUNCATE && in visitVSELECT()
11003 Other.getOperand(0).getOpcode() == ISD::SUB && in visitVSELECT()
11007 if (LHS == OpLHS && RHS == OpRHS && LHS.getOpcode() == ISD::ZERO_EXTEND) in visitVSELECT()
11022 Other.getOpcode() == ISD::SUB && OpRHS == CondRHS) in visitVSELECT()
11025 if (OpRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
11026 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
11027 if (CondRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
11028 CondRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
11037 if (SatCC == ISD::SETUGT && Other.getOpcode() == ISD::ADD && in visitVSELECT()
11051 if (SatCC == ISD::SETLT && Other.getOpcode() == ISD::XOR && in visitVSELECT()
11080 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
11081 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
11128 if (SCC.getOpcode() == ISD::SETCC) { in visitSELECT_CC()
11150 N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND; in visitSETCC()
11188 if (N0->getOpcode() == ISD::FREEZE && N0.hasOneUse() && N1C) { in visitSETCC()
11194 if (N1->getOpcode() == ISD::FREEZE && N1.hasOneUse() && N0C) { in visitSETCC()
11214 if (PreferSetCC && Combined.getOpcode() != ISD::SETCC) { in visitSETCC()
11277 unsigned Opcode = N->getOpcode(); in tryToFoldExtendSelectLoad()
11286 if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) || in tryToFoldExtendSelectLoad()
11320 unsigned Opcode = N->getOpcode(); in tryToFoldExtendOfConstant()
11339 if (N0->getOpcode() == ISD::SELECT) { in tryToFoldExtendOfConstant()
11419 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
11442 if (User->getOpcode() == ISD::CopyToReg) in ExtendUsesToFormExtLoad()
11451 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { in ExtendUsesToFormExtLoad()
11491 assert((N->getOpcode() == ISD::SIGN_EXTEND || in CombineExtLoad()
11492 N->getOpcode() == ISD::ZERO_EXTEND) && in CombineExtLoad()
11512 if (N0->getOpcode() != ISD::LOAD) in CombineExtLoad()
11524 if (!ExtendUsesToFormExtLoad(DstVT, N, N0, N->getOpcode(), SetCCs, TLI)) in CombineExtLoad()
11528 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD; in CombineExtLoad()
11579 ExtendSetCCUses(SetCCs, N0, NewValue, (ISD::NodeType)N->getOpcode()); in CombineExtLoad()
11587 assert(N->getOpcode() == ISD::ZERO_EXTEND); in CombineZExtLogicopShiftLoad()
11595 if (!(N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in CombineZExtLogicopShiftLoad()
11596 N0.getOpcode() == ISD::XOR) || in CombineZExtLogicopShiftLoad()
11597 N0.getOperand(1).getOpcode() != ISD::Constant || in CombineZExtLogicopShiftLoad()
11598 (LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT))) in CombineZExtLogicopShiftLoad()
11603 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) || in CombineZExtLogicopShiftLoad()
11604 N1.getOperand(1).getOpcode() != ISD::Constant || in CombineZExtLogicopShiftLoad()
11605 (LegalOperations && !TLI.isOperationLegal(N1.getOpcode(), VT))) in CombineZExtLogicopShiftLoad()
11620 if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND) in CombineZExtLogicopShiftLoad()
11637 SDValue Shift = DAG.getNode(N1.getOpcode(), DL1, VT, ExtLoad, in CombineZExtLogicopShiftLoad()
11642 SDValue And = DAG.getNode(N0.getOpcode(), DL0, VT, Shift, in CombineZExtLogicopShiftLoad()
11666 unsigned CastOpcode = Cast->getOpcode(); in matchVSelectOpSizesWithSetCC()
11680 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() || in matchVSelectOpSizesWithSetCC()
11681 VSel.getOperand(0).getOpcode() != ISD::SETCC) in matchVSelectOpSizesWithSetCC()
11812 assert((N->getOpcode() == ISD::SIGN_EXTEND || in foldExtendedSignBitTest()
11813 N->getOpcode() == ISD::ZERO_EXTEND) && "Expected sext or zext"); in foldExtendedSignBitTest()
11816 if (LegalOperations || SetCC.getOpcode() != ISD::SETCC || in foldExtendedSignBitTest()
11839 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; in foldExtendedSignBitTest()
11848 if (N0.getOpcode() != ISD::SETCC) in foldSextSetcc()
11922 if (User->getOpcode() != ExtOpcode || User->getValueType(0) != VT) in foldSextSetcc()
11985 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitSIGN_EXTEND()
11988 if (N0.getOpcode() == ISD::TRUNCATE) { in visitSIGN_EXTEND()
12061 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in visitSIGN_EXTEND()
12062 N0.getOpcode() == ISD::XOR) && in visitSIGN_EXTEND()
12064 N0.getOperand(1).getOpcode() == ISD::Constant && in visitSIGN_EXTEND()
12065 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitSIGN_EXTEND()
12079 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitSIGN_EXTEND()
12119 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitSIGN_EXTEND()
12121 N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND && in visitSIGN_EXTEND()
12128 if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && in visitSIGN_EXTEND()
12130 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitSIGN_EXTEND()
12171 if (N->getOpcode() == ISD::TRUNCATE) { in isTruncateOf()
12177 if (N.getOpcode() != ISD::SETCC || in isTruncateOf()
12202 assert((Extend->getOpcode() == ISD::ZERO_EXTEND || in widenCtPop()
12203 Extend->getOpcode() == ISD::ANY_EXTEND) && "Expected extend op"); in widenCtPop()
12206 if (CtPop.getOpcode() != ISD::CTPOP || !CtPop.hasOneUse()) in widenCtPop()
12234 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitZERO_EXTEND()
12256 if (N0.getOpcode() == ISD::TRUNCATE) { in visitZERO_EXTEND()
12300 if (N0.getOpcode() == ISD::AND && in visitZERO_EXTEND()
12301 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitZERO_EXTEND()
12302 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
12334 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in visitZERO_EXTEND()
12335 N0.getOpcode() == ISD::XOR) && in visitZERO_EXTEND()
12337 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
12338 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitZERO_EXTEND()
12346 if (N0.getOpcode() == ISD::AND) { in visitZERO_EXTEND()
12364 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitZERO_EXTEND()
12401 if (N0.getOpcode() == ISD::SETCC) { in visitZERO_EXTEND()
12449 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitZERO_EXTEND()
12451 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitZERO_EXTEND()
12454 if (N0.getOpcode() == ISD::SHL) { in visitZERO_EXTEND()
12470 return DAG.getNode(N0.getOpcode(), DL, VT, in visitZERO_EXTEND()
12501 if (N0.getOpcode() == ISD::ANY_EXTEND || in visitANY_EXTEND()
12502 N0.getOpcode() == ISD::ZERO_EXTEND || in visitANY_EXTEND()
12503 N0.getOpcode() == ISD::SIGN_EXTEND) in visitANY_EXTEND()
12504 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); in visitANY_EXTEND()
12508 if (N0.getOpcode() == ISD::TRUNCATE) { in visitANY_EXTEND()
12521 if (N0.getOpcode() == ISD::TRUNCATE) in visitANY_EXTEND()
12526 if (N0.getOpcode() == ISD::AND && in visitANY_EXTEND()
12527 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitANY_EXTEND()
12528 N0.getOperand(1).getOpcode() == ISD::Constant && in visitANY_EXTEND()
12579 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.getNode()) && in visitANY_EXTEND()
12595 if (N0.getOpcode() == ISD::SETCC) { in visitANY_EXTEND()
12649 unsigned Opcode = N->getOpcode(); in visitAssertExt()
12655 if (N0.getOpcode() == Opcode && in visitAssertExt()
12659 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && in visitAssertExt()
12660 N0.getOperand(0).getOpcode() == Opcode) { in visitAssertExt()
12679 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && in visitAssertExt()
12680 N0.getOperand(0).getOpcode() == ISD::AssertSext && in visitAssertExt()
12710 switch (N0.getOpcode()) { in visitAssertAlign()
12725 return DAG.getNode(N0.getOpcode(), DL, N0.getValueType(), LHS, RHS); in visitAssertAlign()
12738 unsigned Opc = N->getOpcode(); in reduceLoadWidth()
12816 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) { in reduceLoadWidth()
12864 if (SRL.hasOneUse() && Mask->getOpcode() == ISD::AND && in reduceLoadWidth()
12886 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && in reduceLoadWidth()
12994 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in visitSIGN_EXTEND_INREG()
13003 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { in visitSIGN_EXTEND_INREG()
13015 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND_INREG()
13016 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND_INREG()
13017 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) { in visitSIGN_EXTEND_INREG()
13022 bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; in visitSIGN_EXTEND_INREG()
13034 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in visitSIGN_EXTEND_INREG()
13058 if (N0.getOpcode() == ISD::SRL) { in visitSIGN_EXTEND_INREG()
13143 if (ExtVTBits <= 16 && N0.getOpcode() == ISD::OR) { in visitSIGN_EXTEND_INREG()
13180 if (N0.getOpcode() == ISD::TRUNCATE) in visitTRUNCATE()
13191 if (N0.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
13192 N0.getOpcode() == ISD::SIGN_EXTEND || in visitTRUNCATE()
13193 N0.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
13196 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); in visitTRUNCATE()
13207 if (!LegalTypes && N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in visitTRUNCATE()
13219 if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ANY_EXTEND)) in visitTRUNCATE()
13232 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitTRUNCATE()
13258 if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse()) { in visitTRUNCATE()
13270 if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() && in visitTRUNCATE()
13293 if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations && in visitTRUNCATE()
13312 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && in visitTRUNCATE()
13313 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && in visitTRUNCATE()
13339 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { in visitTRUNCATE()
13360 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { in visitTRUNCATE()
13405 if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) { in visitTRUNCATE()
13439 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in visitTRUNCATE()
13441 if (N00.getOpcode() == ISD::SIGN_EXTEND || in visitTRUNCATE()
13442 N00.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
13443 N00.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
13458 switch (N0.getOpcode()) { in visitTRUNCATE()
13471 if (VT.isScalarInteger() || TLI.isOperationLegal(N0.getOpcode(), VT)) { in visitTRUNCATE()
13475 return DAG.getNode(N0.getOpcode(), DL, VT, NarrowL, NarrowR); in visitTRUNCATE()
13485 if (((!LegalOperations && N0.getOpcode() == ISD::ADDCARRY) || in visitTRUNCATE()
13486 TLI.isOperationLegal(N0.getOpcode(), VT)) && in visitTRUNCATE()
13492 return DAG.getNode(N0.getOpcode(), DL, VTs, X, Y, N0.getOperand(2)); in visitTRUNCATE()
13500 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitTRUNCATE()
13503 hasOperation(N0.getOpcode(), VT)) { in visitTRUNCATE()
13515 if (Elt.getOpcode() != ISD::MERGE_VALUES) in getBuildPairElt()
13523 assert(N->getOpcode() == ISD::BUILD_PAIR); in CombineConsecutiveLoads()
13575 switch (N0.getOpcode()) { in foldBitcastedFPLogic()
13599 LogicOp0.getOpcode() == ISD::BITCAST && in foldBitcastedFPLogic()
13603 if (N0.getOpcode() == ISD::OR) in foldBitcastedFPLogic()
13628 N0.getOpcode() == ISD::BUILD_VECTOR && N0->hasOneUse() && in visitBITCAST()
13650 if (N0.getOpcode() == ISD::BITCAST) in visitBITCAST()
13694 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
13695 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && in visitBITCAST()
13707 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
13711 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
13726 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
13729 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
13745 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() && in visitBITCAST()
13809 if (N0.getOpcode() == ISD::BUILD_PAIR) in visitBITCAST()
13818 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && in visitBITCAST()
13826 if (Op.getOpcode() == ISD::BITCAST && in visitBITCAST()
13871 if (N0.getOpcode() == ISD::BITCAST) in visitFREEZE()
13960 assert(N.getOpcode() == ISD::FMUL); in isContractableFMUL()
14008 unsigned Opcode = N.getOpcode(); in visitFADDForFMACombine()
14015 if (N.getOpcode() != ISD::FMUL) in visitFADDForFMACombine()
14044 N0.getOperand(2).getOpcode() == ISD::FMUL && N0.hasOneUse() && in visitFADDForFMACombine()
14049 N1.getOperand(2).getOpcode() == ISD::FMUL && N1.hasOneUse() && in visitFADDForFMACombine()
14066 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14080 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14106 if (N02.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14132 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14150 if (N12.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14167 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14224 if (N.getOpcode() != ISD::FMUL) in visitFSUBForFMACombine()
14269 if (N0.getOpcode() == ISD::FNEG && isContractableFMUL(N0.getOperand(0)) && in visitFSUBForFMACombine()
14282 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14297 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14316 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14318 if (N00.getOpcode() == ISD::FNEG) { in visitFSUBForFMACombine()
14339 if (N0.getOpcode() == ISD::FNEG) { in visitFSUBForFMACombine()
14341 if (N00.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14366 unsigned Opcode = N.getOpcode(); in visitFSUBForFMACombine()
14404 if (N02.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14426 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14448 if (isFusedOp(N1) && N1.getOperand(2).getOpcode() == ISD::FP_EXTEND && in visitFSUBForFMACombine()
14472 if (N1.getOpcode() == ISD::FP_EXTEND && isFusedOp(N1.getOperand(0))) { in visitFSUBForFMACombine()
14507 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation"); in visitFMULForFMADistributiveCombine()
14513 SDValue FAdd = N0.getOpcode() == ISD::FADD ? N0 : N1; in visitFMULForFMADistributiveCombine()
14539 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
14562 if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
14604 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFADD()
14642 if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL) in visitFADD()
14668 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) in visitFADD()
14672 if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) in visitFADD()
14683 if (N1CFP && N0.getOpcode() == ISD::FADD && in visitFADD()
14693 if (N0.getOpcode() == ISD::FMUL) { in visitFADD()
14705 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && in visitFADD()
14714 if (N1.getOpcode() == ISD::FMUL) { in visitFADD()
14726 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD && in visitFADD()
14735 if (N0.getOpcode() == ISD::FADD) { in visitFADD()
14745 if (N1.getOpcode() == ISD::FADD) { in visitFADD()
14756 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && in visitFADD()
14812 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFSUB()
14862 N1.getOpcode() == ISD::FADD) { in visitFSUB()
14895 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFMUL()
14918 N0.getOpcode() == ISD::FMUL) { in visitFMUL()
14932 if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() && in visitFMUL()
14969 (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) && in visitFMUL()
14972 if (Select.getOpcode() != ISD::SELECT) in visitFMUL()
14980 Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == X && in visitFMUL()
15077 if (N2.getOpcode() == ISD::FMUL && N0 == N2.getOperand(0) && in visitFMA()
15085 if (N0.getOpcode() == ISD::FMUL && in visitFMA()
15107 if (N0.getOpcode() == ISD::FNEG && in visitFMA()
15125 if (N1CFP && N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { in visitFMA()
15181 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) { in combineRepeatedFPDivisors()
15183 if (U->getOperand(1).getOpcode() == ISD::FSQRT && in combineRepeatedFPDivisors()
15230 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFDIV()
15270 if (N1.getOpcode() == ISD::FSQRT) { in visitFDIV()
15273 } else if (N1.getOpcode() == ISD::FP_EXTEND && in visitFDIV()
15274 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
15281 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
15282 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
15289 } else if (N1.getOpcode() == ISD::FMUL) { in visitFDIV()
15293 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
15296 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) { in visitFDIV()
15306 if (Y.getOpcode() == ISD::FABS && Y.hasOneUse()) in visitFDIV()
15343 if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0)) in visitFDIV()
15370 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFREM()
15409 if ((N1.getOpcode() == ISD::FP_EXTEND || in CanCombineFCOPYSIGN_EXTEND_ROUND()
15410 N1.getOpcode() == ISD::FP_ROUND)) { in CanCombineFCOPYSIGN_EXTEND_ROUND()
15461 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || in visitFCOPYSIGN()
15462 N0.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
15466 if (N1.getOpcode() == ISD::FABS) in visitFCOPYSIGN()
15470 if (N1.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
15574 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT && in foldFPToIntToFP()
15578 if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT && in foldFPToIntToFP()
15612 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && in visitSINT_TO_FP()
15622 if (N0.getOpcode() == ISD::ZERO_EXTEND && in visitSINT_TO_FP()
15623 N0.getOperand(0).getOpcode() == ISD::SETCC && !VT.isVector() && in visitSINT_TO_FP()
15663 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && in visitUINT_TO_FP()
15681 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP) in FoldIntToFPToInt()
15686 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP; in FoldIntToFPToInt()
15687 bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT; in FoldIntToFPToInt()
15759 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) in visitFP_ROUND()
15763 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
15790 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse()) { in visitFP_ROUND()
15810 N->use_begin()->getOpcode() == ISD::FP_ROUND) in visitFP_EXTEND()
15818 if (N0.getOpcode() == ISD::FP16_TO_FP && in visitFP_EXTEND()
15824 if (N0.getOpcode() == ISD::FP_ROUND in visitFP_EXTEND()
15879 switch (N0.getOpcode()) { in visitFTRUNC()
15920 if (N0.getOpcode() == ISD::FSUB && in visitFNEG()
15938 unsigned Opc = N->getOpcode(); in visitFMinMax()
15950 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0); in visitFMinMax()
15993 if (N0.getOpcode() == ISD::FABS) in visitFABS()
15998 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) in visitFABS()
16014 if (N1->getOpcode() == ISD::FREEZE && N1.hasOneUse()) { in visitBRCOND()
16027 if (N1.getOpcode() == ISD::SETCC && in visitBRCOND()
16048 if (N.getOpcode() == ISD::SRL || in rebuildSetCC()
16049 (N.getOpcode() == ISD::TRUNCATE && in rebuildSetCC()
16051 N.getOperand(0).getOpcode() == ISD::SRL))) { in rebuildSetCC()
16053 if (N.getOpcode() == ISD::TRUNCATE) in rebuildSetCC()
16076 if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == ISD::Constant) { in rebuildSetCC()
16079 if (AndOp1.getOpcode() == ISD::Constant) { in rebuildSetCC()
16095 if (N.getOpcode() == ISD::XOR) { in rebuildSetCC()
16102 while (N.getOpcode() == ISD::XOR) { in rebuildSetCC()
16115 if (N.getOpcode() != ISD::XOR) in rebuildSetCC()
16121 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { in rebuildSetCC()
16124 if (isBitwiseNot(N) && Op0.hasOneUse() && Op0.getOpcode() == ISD::XOR && in rebuildSetCC()
16163 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) in visitBR_CC()
16233 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || in CombineToPreIndexedLoadStore()
16306 if (Use.getUser()->getOpcode() != ISD::ADD && in CombineToPreIndexedLoadStore()
16307 Use.getUser()->getOpcode() != ISD::SUB) { in CombineToPreIndexedLoadStore()
16403 int X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1; in CombineToPreIndexedLoadStore()
16404 int Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1; in CombineToPreIndexedLoadStore()
16442 (PtrUse->getOpcode() != ISD::ADD && PtrUse->getOpcode() != ISD::SUB)) in shouldCombineToPostInc()
16476 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB) { in shouldCombineToPostInc()
16583 assert((Inc.getOpcode() != ISD::TargetConstant || in SplitIndexingFromLoad()
16586 if (Inc.getOpcode() == ISD::TargetConstant) { in SplitIndexingFromLoad()
17166 if (Use->getOpcode() != ISD::BITCAST) in canMergeExpensiveCrossRegisterBankCopy()
17384 if (User->getOpcode() == ISD::SRL && User->hasOneUse() && in SliceUpLoad()
17392 if (User->getOpcode() != ISD::TRUNCATE) in SliceUpLoad()
17435 if (SliceInst.getOpcode() != ISD::LOAD) in SliceUpLoad()
17437 assert(SliceInst->getOpcode() == ISD::LOAD && in SliceUpLoad()
17457 if (V->getOpcode() != ISD::AND || in CheckForMaskedLoad()
17506 else if (Chain->getOpcode() == ISD::TokenFactor && in CheckForMaskedLoad()
17610 unsigned Opc = Value.getOpcode(); in ReduceLoadOpStoreWidth()
17640 if (Value.getOperand(1).getOpcode() != ISD::Constant) in ReduceLoadOpStoreWidth()
17811 if (Use->getOpcode() == ISD::MUL) { // We have another multiply use. in isMulAddWithConstProfitable()
17847 if (OtherOp->getOpcode() == ISD::ADD && in isMulAddWithConstProfitable()
17964 (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in mergeStoresOfConstantsOrVecElts()
17965 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in mergeStoresOfConstantsOrVecElts()
18138 if (OtherBC.getOpcode() != ISD::EXTRACT_VECTOR_ELT && in getStoreMergeCandidates()
18139 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) in getStoreMergeCandidates()
18235 if (N->getOpcode() == ISD::TokenFactor) { in checkMergeStoreCandidatesForDependencies()
18919 if (Value.getOpcode() == ISD::TargetConstantFP) in replaceStoreOfFPConstant()
19003 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && in visitSTORE()
19067 if ((Value.getOpcode() == ISD::ZERO_EXTEND || in visitSTORE()
19068 Value.getOpcode() == ISD::SIGN_EXTEND || in visitSTORE()
19069 Value.getOpcode() == ISD::ANY_EXTEND) && in visitSTORE()
19094 if (N->getOpcode() != ISD::DELETED_NODE) in visitSTORE()
19152 if ((Value.getOpcode() == ISD::FP_ROUND || in visitSTORE()
19153 Value.getOpcode() == ISD::TRUNCATE) && in visitSTORE()
19173 if (N->getOpcode() == ISD::DELETED_NODE || !isa<StoreSDNode>(N)) in visitSTORE()
19212 switch (Chain.getOpcode()) { in visitLIFETIME_END()
19292 if (!Val.getValueType().isScalarInteger() || Val.getOpcode() != ISD::OR) in splitMergedValStore()
19299 if (Op1.getOpcode() != ISD::SHL) { in splitMergedValStore()
19301 if (Op1.getOpcode() != ISD::SHL) in splitMergedValStore()
19317 if (Lo.getOpcode() != ISD::ZERO_EXTEND || !Lo.hasOneUse() || in splitMergedValStore()
19320 Hi.getOpcode() != ISD::ZERO_EXTEND || !Hi.hasOneUse() || in splitMergedValStore()
19327 EVT LowTy = (Lo.getOperand(0).getOpcode() == ISD::BITCAST) in splitMergedValStore()
19330 EVT HighTy = (Hi.getOperand(0).getOpcode() == ISD::BITCAST) in splitMergedValStore()
19360 assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && in combineInsertEltToShuffle()
19369 if (Vec.getOpcode() == ISD::VECTOR_SHUFFLE && Vec.hasOneUse() && in combineInsertEltToShuffle()
19370 InsertVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineInsertEltToShuffle()
19402 if (ArgVal.getOpcode() == ISD::CONCAT_VECTORS) { in combineInsertEltToShuffle()
19446 if (InsertVal.getOpcode() != ISD::BITCAST || !InsertVal.hasOneUse() || in combineInsertEltToShuffle()
19513 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
19544 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
19557 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
19612 if (CurVec.getOpcode() == ISD::BUILD_VECTOR && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
19619 if (CurVec.getOpcode() == ISD::SCALAR_TO_VECTOR && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
19625 if (CurVec.getOpcode() == ISD::INSERT_VECTOR_ELT && CurVec.hasOneUse()) in visitINSERT_VECTOR_ELT()
19730 if (!IndexC || !TLI.isBinOp(Vec.getOpcode()) || !Vec.hasOneUse() || in scalarizeExtractedBinop()
19754 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); in scalarizeExtractedBinop()
19773 if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
19780 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
19804 if (((IndexC && VecOp.getOpcode() == ISD::BUILD_VECTOR) || in visitEXTRACT_VECTOR_ELT()
19805 VecOp.getOpcode() == ISD::SPLAT_VECTOR) && in visitEXTRACT_VECTOR_ELT()
19808 assert((VecOp.getOpcode() != ISD::BUILD_VECTOR || in visitEXTRACT_VECTOR_ELT()
19812 VecOp.getOpcode() == ISD::BUILD_VECTOR ? IndexC->getZExtValue() : 0; in visitEXTRACT_VECTOR_ELT()
19839 if (IndexC && VecOp.getOpcode() == ISD::BITCAST && VecVT.isInteger() && in visitEXTRACT_VECTOR_ELT()
19851 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
19878 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
19896 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) { in visitEXTRACT_VECTOR_ELT()
19921 return Use->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
19934 if (N->getOpcode() != ISD::DELETED_NODE) in visitEXTRACT_VECTOR_ELT()
19942 if (N->getOpcode() != ISD::DELETED_NODE) in visitEXTRACT_VECTOR_ELT()
19957 if (VecOp.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
19992 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
20019 if (VecOp.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
20031 } else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS && !BCNumEltsChanged && in visitEXTRACT_VECTOR_ELT()
20097 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; in reduceBuildVecExtToExtBuildVec()
20098 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; in reduceBuildVecExtToExtBuildVec()
20153 assert((Cast.getOpcode() == ISD::ANY_EXTEND || in reduceBuildVecExtToExtBuildVec()
20154 Cast.getOpcode() == ISD::ZERO_EXTEND || in reduceBuildVecExtToExtBuildVec()
20192 assert(N->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); in reduceBuildVecTruncToBitCast()
20211 if (Op.getOpcode() == ISD::BITCAST) in reduceBuildVecTruncToBitCast()
20223 if (In.getOpcode() != ISD::TRUNCATE) in reduceBuildVecTruncToBitCast()
20228 if (In.getOpcode() != ISD::SRL) { in reduceBuildVecTruncToBitCast()
20385 assert(BV->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); in reduceBuildVecToShuffleWithZero()
20412 if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() || in reduceBuildVecToShuffleWithZero()
20413 Zext.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffleWithZero()
20518 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffle()
20693 bool IsLeftShuffle = L.getOpcode() == ISD::VECTOR_SHUFFLE && in reduceBuildVecToShuffle()
20702 bool IsRightShuffle = R.getOpcode() == ISD::VECTOR_SHUFFLE && in reduceBuildVecToShuffle()
20742 unsigned Opc = Op.getOpcode(); in convertBuildVecZextToZext()
20745 Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT && in convertBuildVecZextToZext()
20819 if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) && in visitBUILD_VECTOR()
20886 if (ISD::BITCAST == Op.getOpcode() && in combineConcatVectorOfScalars()
20889 else if (ISD::UNDEF == Op.getOpcode()) in combineConcatVectorOfScalars()
20941 if (Op.getOpcode() != ISD::CONCAT_VECTORS) in combineConcatVectorOfConcatVectors()
20993 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in combineConcatVectorOfExtracts()
21045 unsigned CastOpcode = N->getOperand(0).getOpcode(); in combineConcatVectorOfCasts()
21070 if (Op.getOpcode() != CastOpcode || !Op.hasOneUse() || in combineConcatVectorOfCasts()
21125 if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse()) { in visitCONCAT_VECTORS()
21136 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitCONCAT_VECTORS()
21148 if (Scalar->getOpcode() == ISD::TRUNCATE && in visitCONCAT_VECTORS()
21180 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode(); in visitCONCAT_VECTORS()
21192 if (ISD::BUILD_VECTOR == Op.getOpcode()) { in visitCONCAT_VECTORS()
21204 if (ISD::UNDEF == Op.getOpcode()) in visitCONCAT_VECTORS()
21207 if (ISD::BUILD_VECTOR == Op.getOpcode()) { in visitCONCAT_VECTORS()
21259 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in visitCONCAT_VECTORS()
21291 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && in getSubVectorSrc()
21296 if (IndexC && V.getOpcode() == ISD::CONCAT_VECTORS && in getSubVectorSrc()
21310 unsigned BinOpcode = BinOp.getOpcode(); in narrowInsertExtractVectorBinOp()
21359 unsigned BOpcode = BinOp.getOpcode(); in narrowExtractedVectorBinOp()
21440 if (V.getOpcode() == ISD::CONCAT_VECTORS && V.getNumOperands() == 2) in narrowExtractedVectorBinOp()
21538 assert(N->getOpcode() == ISD::EXTRACT_SUBVECTOR && in foldExtractSubvectorFromShuffleVector()
21692 if (ExtIdx == 0 && V.getOpcode() == ISD::EXTRACT_SUBVECTOR && V.hasOneUse()) { in visitEXTRACT_SUBVECTOR()
21702 if (V.getOpcode() == ISD::SPLAT_VECTOR) in visitEXTRACT_SUBVECTOR()
21709 if (V.getOpcode() == ISD::BITCAST && in visitEXTRACT_SUBVECTOR()
21760 if (V.getOpcode() == ISD::CONCAT_VECTORS) { in visitEXTRACT_SUBVECTOR()
21803 if (V.getOpcode() == ISD::BUILD_VECTOR) { in visitEXTRACT_SUBVECTOR()
21835 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
21877 if (N0.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 || in foldShuffleOfConcatUndefs()
21878 N1.getOpcode() != ISD::CONCAT_VECTORS || N1.getNumOperands() != 2 || in foldShuffleOfConcatUndefs()
22042 if (S.getOpcode() == ISD::BUILD_VECTOR) { in combineShuffleOfScalars()
22044 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) { in combineShuffleOfScalars()
22151 unsigned Opcode = N0.getOpcode(); in combineTruncationShuffle()
22267 if (Op0.getOpcode() != ISD::BITCAST) in combineShuffleOfBitcast()
22271 (!Op1.isUndef() && (Op1.getOpcode() != ISD::BITCAST || in combineShuffleOfBitcast()
22411 if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceShuffleOfInsert()
22516 TLI.isBinOp(N0.getOpcode()) && N0->getNumValues() == 1) { in visitVECTOR_SHUFFLE()
22526 DAG.getNode(N0.getOpcode(), DL, EltVT, ExtL, ExtR, N0->getFlags()); in visitVECTOR_SHUFFLE()
22536 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && SplatIndex == 0) in visitVECTOR_SHUFFLE()
22539 if (N0.getOpcode() == ISD::INSERT_VECTOR_ELT) in visitVECTOR_SHUFFLE()
22549 if (V->getOpcode() == ISD::BITCAST) { in visitVECTOR_SHUFFLE()
22556 if (V->getOpcode() == ISD::BUILD_VECTOR) { in visitVECTOR_SHUFFLE()
22610 if (N0.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
22613 (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
22622 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N1.isUndef() && in visitVECTOR_SHUFFLE()
22651 assert(RHS.getOpcode() == ISD::CONCAT_VECTORS && "Can't find subvectors"); in visitVECTOR_SHUFFLE()
22696 if (N1.getOpcode() == ISD::CONCAT_VECTORS) in visitVECTOR_SHUFFLE()
22699 if (N0.getOpcode() == ISD::CONCAT_VECTORS) { in visitVECTOR_SHUFFLE()
22773 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && in visitVECTOR_SHUFFLE()
22778 if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) { in visitVECTOR_SHUFFLE()
22952 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
22953 N0.getOpcode() != ISD::VECTOR_SHUFFLE) { in visitVECTOR_SHUFFLE()
22970 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
22971 N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
22985 if (N->getOperand(i).getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
23012 unsigned SrcOpcode = N0.getOpcode(); in visitVECTOR_SHUFFLE()
23015 (SrcOpcode == N1.getOpcode() && N->isOnlyUserOf(N1.getNode())))) { in visitVECTOR_SHUFFLE()
23026 (Op00.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
23027 Op10.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
23028 Op01.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
23029 Op11.getOpcode() == ISD::VECTOR_SHUFFLE)) { in visitVECTOR_SHUFFLE()
23098 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitSCALAR_TO_VECTOR()
23157 if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in visitINSERT_SUBVECTOR()
23163 if (N0.isUndef() && N1.getOpcode() == ISD::SPLAT_VECTOR) in visitINSERT_SUBVECTOR()
23170 if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST && in visitINSERT_SUBVECTOR()
23171 N1.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR && in visitINSERT_SUBVECTOR()
23184 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) { in visitINSERT_SUBVECTOR()
23201 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
23210 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
23218 if ((N0.isUndef() || N0.getOpcode() == ISD::BITCAST) && in visitINSERT_SUBVECTOR()
23219 N1.getOpcode() == ISD::BITCAST) { in visitINSERT_SUBVECTOR()
23256 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
23271 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
23292 if (N0->getOpcode() == ISD::FP16_TO_FP) in visitFP_TO_FP16()
23302 if (!TLI.shouldKeepZExtForFP16Conv() && N0->getOpcode() == ISD::AND) { in visitFP16_TO_FP()
23317 if (N0->getOpcode() == ISD::BF16_TO_FP) in visitFP_TO_BF16()
23326 unsigned Opcode = N->getOpcode(); in visitVECREDUCE()
23352 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitVECREDUCE()
23371 if (auto EVLIdx = ISD::getVPExplicitVectorLengthIdx(N->getOpcode())) in visitVPOp()
23373 if (auto MaskIdx = ISD::getVPMaskIdx(N->getOpcode())) in visitVPOp()
23382 if (ISD::isVPBinaryOp(N->getOpcode())) in visitVPOp()
23394 if (ISD::isVPReduction(N->getOpcode())) in visitVPOp()
23405 assert(N->getOpcode() == ISD::AND && "Unexpected opcode!"); in XformToShuffleWithZero()
23417 if (RHS.getOpcode() != ISD::BUILD_VECTOR) in XformToShuffleWithZero()
23495 unsigned Opcode = N->getOpcode(); in scalarizeBinOpOfSplats()
23508 bool IsBothSplatVector = N0.getOpcode() == ISD::SPLAT_VECTOR && in scalarizeBinOpOfSplats()
23509 N1.getOpcode() == ISD::SPLAT_VECTOR; in scalarizeBinOpOfSplats()
23524 if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode() && in scalarizeBinOpOfSplats()
23548 unsigned Opcode = N->getOpcode(); in SimplifyVBinOp()
23580 Shuf0->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { in SimplifyVBinOp()
23589 Shuf1->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { in SimplifyVBinOp()
23602 if (LHS.getOpcode() == ISD::INSERT_SUBVECTOR && LHS.getOperand(0).isUndef() && in SimplifyVBinOp()
23603 RHS.getOpcode() == ISD::INSERT_SUBVECTOR && RHS.getOperand(0).isUndef() && in SimplifyVBinOp()
23623 return Concat.getOpcode() == ISD::CONCAT_VECTORS && in SimplifyVBinOp()
23660 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); in SimplifySelect()
23671 if (SCC.getOpcode() == ISD::SELECT_CC) { in SimplifySelect()
23699 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) { in SimplifySelectOps()
23706 if (TheSelect->getOpcode() == ISD::SELECT_CC) { in SimplifySelectOps()
23713 if (Cmp.getOpcode() == ISD::SETCC) { in SimplifySelectOps()
23733 if (LHS.getOpcode() != RHS.getOpcode() || in SimplifySelectOps()
23741 if (LHS.getOpcode() == ISD::LOAD) { in SimplifySelectOps()
23770 LLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || in SimplifySelectOps()
23771 RLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || in SimplifySelectOps()
23772 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(), in SimplifySelectOps()
23799 if (TheSelect->getOpcode() == ISD::SELECT) { in SimplifySelectOps()
23962 unsigned BinOpc = N1.getOpcode(); in foldSelectOfBinops()
23963 if (!TLI.isBinOp(BinOpc) || (N2.getOpcode() != BinOpc)) in foldSelectOfBinops()
24010 bool IsFabs = N->getOpcode() == ISD::FABS; in foldSignChangeInBitcast()
24013 if (IsFree || N0.getOpcode() != ISD::BITCAST || !N0.hasOneUse()) in foldSignChangeInBitcast()
24141 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && in SimplifySelectCC()
24234 if ((Count.getOpcode() == ISD::CTTZ || in SimplifySelectCC()
24235 Count.getOpcode() == ISD::CTTZ_ZERO_UNDEF) && in SimplifySelectCC()
24241 if ((Count.getOpcode() == ISD::CTLZ || in SimplifySelectCC()
24242 Count.getOpcode() == ISD::CTLZ_ZERO_UNDEF) && in SimplifySelectCC()
24728 switch (C.getOpcode()) { in GatherAllAliases()
24791 if (Chain.getOpcode() == ISD::TokenFactor) { in GatherAllAliases()