Lines Matching refs:getOpcode
37 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; in isVector()
139 if (isALUInstr(MI.getOpcode())) in canBeConsideredALU()
141 if (isVector(MI) || isCubeOp(MI.getOpcode())) in canBeConsideredALU()
143 switch (MI.getOpcode()) { in canBeConsideredALU()
163 return isTransOnly(MI.getOpcode()); in isTransOnly()
171 return isVectorOnly(MI.getOpcode()); in isVectorOnly()
185 usesVertexCache(MI.getOpcode()); in usesVertexCache()
195 usesVertexCache(MI.getOpcode())) || in usesTextureCache()
196 usesTextureCache(MI.getOpcode()); in usesTextureCache()
218 if (!isALUInstr(MI.getOpcode())) { in readsLDSSrcReg()
260 if (MI.getOpcode() == R600::DOT_4) { in getSrcs()
273 MachineOperand &MO = MI.getOperand(getOperandIdx(MI.getOpcode(), Op[0])); in getSrcs()
277 MI.getOperand(getOperandIdx(MI.getOpcode(), Op[1])); in getSrcs()
292 int SrcIdx = getOperandIdx(MI.getOpcode(), Op[0]); in getSrcs()
298 MachineOperand &Sel = MI.getOperand(getOperandIdx(MI.getOpcode(), Op[1])); in getSrcs()
304 MI.getOperand(getOperandIdx(MI.getOpcode(), R600::OpName::literal)); in getSrcs()
524 unsigned Op = getOperandIdx(MI->getOpcode(), R600::OpName::bank_swizzle); in fitsReadPortLimitations()
587 if (!isALUInstr(MI->getOpcode())) in fitsConstReadLimitations()
630 if (isPredicateSetter(MI.getOpcode())) in findFirstPredicateSetterFrom()
661 if (isBranch(I->getOpcode())) in analyzeBranch()
663 if (!isJump(I->getOpcode())) { in analyzeBranch()
668 while (I != MBB.begin() && std::prev(I)->getOpcode() == R600::JUMP) { in analyzeBranch()
677 unsigned LastOpc = LastInst.getOpcode(); in analyzeBranch()
678 if (I == MBB.begin() || !isJump((--I)->getOpcode())) { in analyzeBranch()
684 while (!isPredicateSetter(predSet->getOpcode())) { in analyzeBranch()
698 unsigned SecondLastOpc = SecondLastInst.getOpcode(); in analyzeBranch()
703 while (!isPredicateSetter(predSet->getOpcode())) { in analyzeBranch()
722 if (It->getOpcode() == R600::CF_ALU || in FindLastAluClause()
723 It->getOpcode() == R600::CF_ALU_PUSH_BEFORE) in FindLastAluClause()
754 assert (CfAlu->getOpcode() == R600::CF_ALU); in insertBranch()
770 assert (CfAlu->getOpcode() == R600::CF_ALU); in insertBranch()
789 switch (I->getOpcode()) { in removeBranch()
799 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE); in removeBranch()
813 switch (I->getOpcode()) { in removeBranch()
824 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE); in removeBranch()
856 if (MI.getOpcode() == R600::KILLGT) { in isPredicable()
858 } else if (MI.getOpcode() == R600::CF_ALU) { in isPredicable()
942 return isPredicateSetter(MI.getOpcode()); in ClobbersPredicate()
949 if (MI.getOpcode() == R600::CF_ALU) { in PredicateInstruction()
954 if (MI.getOpcode() == R600::DOT_4) { in PredicateInstruction()
998 switch (MI.getOpcode()) { in expandPostRAPseudo()
1002 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::addr); in expandPostRAPseudo()
1007 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::chan); in expandPostRAPseudo()
1010 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::dst); in expandPostRAPseudo()
1024 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::val); in expandPostRAPseudo()
1293 assert (MI->getOpcode() == R600::DOT_4 && "Not Implemented"); in buildSlotOfVectorInstruction()
1301 getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src0, Slot))); in buildSlotOfVectorInstruction()
1303 getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src1, Slot))); in buildSlotOfVectorInstruction()
1323 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(), in buildSlotOfVectorInstruction()
1330 getOperandIdx(MI->getOpcode(), getSlotedOps(Operand, Slot))); in buildSlotOfVectorInstruction()
1355 return getOperandIdx(MI.getOpcode(), Op); in getOperandIdx()
1376 unsigned TargetFlags = get(MI.getOpcode()).TSFlags; in getFlagOp()
1441 unsigned TargetFlags = get(MI.getOpcode()).TSFlags; in addFlag()
1462 unsigned TargetFlags = get(MI.getOpcode()).TSFlags; in clearFlag()