Lines Matching refs:getOpcode
59 return Inst.getOpcode() == AArch64::ADRP; in isADRP()
63 return Inst.getOpcode() == AArch64::ADR; in isADR()
76 return (Inst.getOpcode() == AArch64::TBNZW || in isTB()
77 Inst.getOpcode() == AArch64::TBNZX || in isTB()
78 Inst.getOpcode() == AArch64::TBZW || in isTB()
79 Inst.getOpcode() == AArch64::TBZX); in isTB()
83 return (Inst.getOpcode() == AArch64::CBNZW || in isCB()
84 Inst.getOpcode() == AArch64::CBNZX || in isCB()
85 Inst.getOpcode() == AArch64::CBZW || in isCB()
86 Inst.getOpcode() == AArch64::CBZX); in isCB()
90 return (Inst.getOpcode() == AArch64::MOVKWi || in isMOVW()
91 Inst.getOpcode() == AArch64::MOVKXi || in isMOVW()
92 Inst.getOpcode() == AArch64::MOVNWi || in isMOVW()
93 Inst.getOpcode() == AArch64::MOVNXi || in isMOVW()
94 Inst.getOpcode() == AArch64::MOVZXi || in isMOVW()
95 Inst.getOpcode() == AArch64::MOVZWi); in isMOVW()
99 return (Inst.getOpcode() == AArch64::ADDSWri || in isADD()
100 Inst.getOpcode() == AArch64::ADDSWrr || in isADD()
101 Inst.getOpcode() == AArch64::ADDSWrs || in isADD()
102 Inst.getOpcode() == AArch64::ADDSWrx || in isADD()
103 Inst.getOpcode() == AArch64::ADDSXri || in isADD()
104 Inst.getOpcode() == AArch64::ADDSXrr || in isADD()
105 Inst.getOpcode() == AArch64::ADDSXrs || in isADD()
106 Inst.getOpcode() == AArch64::ADDSXrx || in isADD()
107 Inst.getOpcode() == AArch64::ADDSXrx64 || in isADD()
108 Inst.getOpcode() == AArch64::ADDWri || in isADD()
109 Inst.getOpcode() == AArch64::ADDWrr || in isADD()
110 Inst.getOpcode() == AArch64::ADDWrs || in isADD()
111 Inst.getOpcode() == AArch64::ADDWrx || in isADD()
112 Inst.getOpcode() == AArch64::ADDXri || in isADD()
113 Inst.getOpcode() == AArch64::ADDXrr || in isADD()
114 Inst.getOpcode() == AArch64::ADDXrs || in isADD()
115 Inst.getOpcode() == AArch64::ADDXrx || in isADD()
116 Inst.getOpcode() == AArch64::ADDXrx64); in isADD()
120 return (Inst.getOpcode() == AArch64::LDRBBpost || in isLDRB()
121 Inst.getOpcode() == AArch64::LDRBBpre || in isLDRB()
122 Inst.getOpcode() == AArch64::LDRBBroW || in isLDRB()
123 Inst.getOpcode() == AArch64::LDRBBroX || in isLDRB()
124 Inst.getOpcode() == AArch64::LDRBBui || in isLDRB()
125 Inst.getOpcode() == AArch64::LDRSBWpost || in isLDRB()
126 Inst.getOpcode() == AArch64::LDRSBWpre || in isLDRB()
127 Inst.getOpcode() == AArch64::LDRSBWroW || in isLDRB()
128 Inst.getOpcode() == AArch64::LDRSBWroX || in isLDRB()
129 Inst.getOpcode() == AArch64::LDRSBWui || in isLDRB()
130 Inst.getOpcode() == AArch64::LDRSBXpost || in isLDRB()
131 Inst.getOpcode() == AArch64::LDRSBXpre || in isLDRB()
132 Inst.getOpcode() == AArch64::LDRSBXroW || in isLDRB()
133 Inst.getOpcode() == AArch64::LDRSBXroX || in isLDRB()
134 Inst.getOpcode() == AArch64::LDRSBXui); in isLDRB()
138 return (Inst.getOpcode() == AArch64::LDRHHpost || in isLDRH()
139 Inst.getOpcode() == AArch64::LDRHHpre || in isLDRH()
140 Inst.getOpcode() == AArch64::LDRHHroW || in isLDRH()
141 Inst.getOpcode() == AArch64::LDRHHroX || in isLDRH()
142 Inst.getOpcode() == AArch64::LDRHHui || in isLDRH()
143 Inst.getOpcode() == AArch64::LDRSHWpost || in isLDRH()
144 Inst.getOpcode() == AArch64::LDRSHWpre || in isLDRH()
145 Inst.getOpcode() == AArch64::LDRSHWroW || in isLDRH()
146 Inst.getOpcode() == AArch64::LDRSHWroX || in isLDRH()
147 Inst.getOpcode() == AArch64::LDRSHWui || in isLDRH()
148 Inst.getOpcode() == AArch64::LDRSHXpost || in isLDRH()
149 Inst.getOpcode() == AArch64::LDRSHXpre || in isLDRH()
150 Inst.getOpcode() == AArch64::LDRSHXroW || in isLDRH()
151 Inst.getOpcode() == AArch64::LDRSHXroX || in isLDRH()
152 Inst.getOpcode() == AArch64::LDRSHXui); in isLDRH()
156 return (Inst.getOpcode() == AArch64::LDRWpost || in isLDRW()
157 Inst.getOpcode() == AArch64::LDRWpre || in isLDRW()
158 Inst.getOpcode() == AArch64::LDRWroW || in isLDRW()
159 Inst.getOpcode() == AArch64::LDRWroX || in isLDRW()
160 Inst.getOpcode() == AArch64::LDRWui); in isLDRW()
164 return (Inst.getOpcode() == AArch64::LDRXpost || in isLDRX()
165 Inst.getOpcode() == AArch64::LDRXpre || in isLDRX()
166 Inst.getOpcode() == AArch64::LDRXroW || in isLDRX()
167 Inst.getOpcode() == AArch64::LDRXroX || in isLDRX()
168 Inst.getOpcode() == AArch64::LDRXui); in isLDRX()
178 const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode()); in isLoadFromStack()
194 if (Inst.getOpcode() != AArch64::ORRXrs) in isRegToRegMove()
206 return Inst.getOpcode() == AArch64::BLR; in isIndirectCall()
220 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); in hasPCRelOperand()
240 if (Inst.getOpcode() == AArch64::ADR) { in evaluateADR()
254 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); in evaluateAArch64MemoryOperand()
285 if (Inst.getOpcode() == AArch64::ADRP) in evaluateMemOperandTarget()
299 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); in replaceMemOperandDisp()
409 if (BinExpr && BinExpr->getOpcode() == MCBinaryExpr::Add) in getTargetAddend()
447 if (Info->get(Inst.getOpcode()).OpInfo[OpNum].OperandType != in evaluateBranch()
503 assert(Inst.getOpcode() == AArch64::BR && "Unexpected opcode"); in analyzeIndirectBranchFragment()
518 if (DefAdd->getOpcode() == AArch64::ADDXri) { in analyzeIndirectBranchFragment()
526 if (DefAdd->getOpcode() == AArch64::ADDXrs) { in analyzeIndirectBranchFragment()
542 assert(DefAdd->getOpcode() == AArch64::ADDXrx && in analyzeIndirectBranchFragment()
571 assert(DefBaseAddr->getOpcode() == AArch64::ADR && in analyzeIndirectBranchFragment()
596 assert(DefJTBaseAdd->getOpcode() == AArch64::ADDXri && in analyzeIndirectBranchFragment()
607 assert(DefJTBasePage->getOpcode() == AArch64::ADRP && in analyzeIndirectBranchFragment()
722 assert(Branch->getOpcode() == AArch64::BR && "Unexpected opcode"); in analyzePLTEntry()
734 if (Ldr->getOpcode() != AArch64::LDRXui) in analyzePLTEntry()
749 if (Adrp->getOpcode() != AArch64::ADRP) in analyzePLTEntry()
790 return Inst.getOpcode(); in getCondCode()
807 Inst.setOpcode(getInvertedBranchOpcode(Inst.getOpcode())); in reverseBranchCondition()
808 assert(Inst.getOpcode() != 0 && "Invalid branch instruction"); in reverseBranchCondition()
809 } else if (Inst.getOpcode() == AArch64::Bcc) { in reverseBranchCondition()
823 switch (Inst.getOpcode()) { in getPCRelEncodingSize()
888 return Inst.getOpcode() == AArch64::HINT && in isNoop()
1039 if (CurInst.getOpcode() != AArch64::BR || !CurInst.getOperand(0).isReg() || in matchLinkerVeneer()
1049 if (I == Begin || I->getOpcode() != AArch64::ADDXri || in matchLinkerVeneer()
1060 if (I->getOpcode() != AArch64::ADRP || in matchLinkerVeneer()