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Searched refs:getNode (Results 1 – 25 of 226) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1428 SDValue Hi = DAG.getNode( in splitVector()
1482 Join = DAG.getNode( in SplitVectorLoad()
1927 Z = DAG.getNode(ISD::ADD, DL, VT, Z, in LowerUDIVREM()
1933 DAG.getNode(ISD::SUB, DL, VT, X, DAG.getNode(ISD::MUL, DL, VT, Q, Y)); in LowerUDIVREM()
2348 SDValue OppositeSign = DAG.getNode( in LowerINT_TO_FP32()
3028 DCI.AddToWorklist(Lo.getNode()); in splitBinaryBitConstantOpImpl()
3029 DCI.AddToWorklist(Hi.getNode()); in splitBinaryBitConstantOpImpl()
3157 return DAG.getNode( in performSrlCombine()
3418 DCI.AddToWorklist(Mulhi.getNode()); in performMulhsCombine()
3451 DCI.AddToWorklist(Mulhi.getNode()); in performMulhuCombine()
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H A DAMDGPUHSAMetadataStreamer.cpp608 Dims.push_back(Dims.getDocument()->getNode( in getWorkGroupDimensions()
628 Printf.push_back(Printf.getDocument()->getNode( in emitPrintf()
645 LanguageVersion.push_back(Kern.getDocument()->getNode( in emitKernelLanguage()
647 LanguageVersion.push_back(Kern.getDocument()->getNode( in emitKernelLanguage()
660 Kern[".vec_type_hint"] = Kern.getDocument()->getNode( in emitKernelAttrs()
672 Kern[".kind"] = Kern.getDocument()->getNode("init"); in emitKernelAttrs()
674 Kern[".kind"] = Kern.getDocument()->getNode("fini"); in emitKernelAttrs()
761 Arg[".size"] = Arg.getDocument()->getNode(Size); in emitKernelArg()
763 Arg[".offset"] = Arg.getDocument()->getNode(Offset); in emitKernelArg()
875 Kern.getDocument()->getNode(ProgramInfo.LDSSize); in getHSAKernelProps()
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H A DR600ISelLowering.cpp412 assert((!Result.getNode() || in LowerOperation()
690 DAG.getNode(ISD::FADD, DL, VT, in LowerTrig()
742 return DAG.getNode( in lowerFP_TO_UINT()
752 return DAG.getNode( in lowerFP_TO_SINT()
1838 if (LHS.getOperand(2).getNode() != True.getNode() || in PerformDAGCombine()
1839 LHS.getOperand(3).getNode() != False.getNode() || in PerformDAGCombine()
1840 RHS.getNode() != False.getNode()) { in PerformDAGCombine()
1937 if (!Neg.getNode()) in FoldOperand()
1943 if (!Abs.getNode()) in FoldOperand()
1952 if (!Sel.getNode()) in FoldOperand()
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/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVECustomDAG.cpp219 if (MemSDNode *MemN = dyn_cast<MemSDNode>(Op.getNode())) in getNodeChain()
231 if (auto *MemN = dyn_cast<MemSDNode>(Op.getNode())) in getMemoryPtr()
305 if (isa<MemSDNode>(Op.getNode())) { in getLoadStoreStride()
338 if (auto *StoreN = dyn_cast<StoreSDNode>(Op.getNode())) in getStoredValue()
354 if (auto *N = dyn_cast<MaskedLoadSDNode>(Op.getNode())) in getNodePassthru()
465 Scalar = getNode(VEISD::REPL_F32, MVT::i64, Scalar); in getBroadcast()
467 Scalar = getNode(VEISD::REPL_I32, MVT::i64, Scalar); in getBroadcast()
487 return DAG.getNode(OC, DL, DestVT, Vec, AVL); in getUnpack()
504 NewAVL = getNode(ISD::ADD, MVT::i32, {RawAVL, OneV}); in getTargetSplitMask()
507 NewAVL = getNode(ISD::SRL, MVT::i32, {NewAVL, OneV}); in getTargetSplitMask()
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H A DVVPISelLowering.cpp33 auto LoRes = CDAG.getNode(Opc, MVT::v256i1, {LoA, LoB}); in splitMaskArithmetic()
34 auto HiRes = CDAG.getNode(Opc, MVT::v256i1, {HiA, HiB}); in splitMaskArithmetic()
59 EVT OpVecVT = *getIdiomaticVectorType(Op.getNode()); in lowerToVVP()
86 return CDAG.getNode(VVPOpcode, LegalVecVT, in lowerToVVP()
140 auto DataVT = *getIdiomaticVectorType(Op.getNode()); in lowerVVP_LOAD_STORE()
162 SDValue DataV = CDAG.getNode(VEISD::VVP_SELECT, DataVT, in lowerVVP_LOAD_STORE()
164 SDValue NewLoadChainV = SDValue(NewLoadV.getNode(), 1); in lowerVVP_LOAD_STORE()
172 return CDAG.getNode(VEISD::VVP_STORE, Op.getNode()->getVTList(), in lowerVVP_LOAD_STORE()
265 EVT DataVT = *getIdiomaticVectorType(Op.getNode()); in lowerVVP_GATHER_SCATTER()
294 return CDAG.getNode(VEISD::VVP_SCATTER, MVT::Other, in lowerVVP_GATHER_SCATTER()
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/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1322 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); in SExtPromoteOperand()
3237 if (Carry1.getNode()->isOperandOf(Carry0.getNode())) in combineCarryDiamond()
4857 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && in SimplifyNodeWithTwoResults()
7593 if (LHSMask.getNode() || RHSMask.getNode()) { in MatchRotate()
7686 if (LHSMask.getNode() || RHSMask.getNode()) in MatchRotate()
11993 if (NarrowLoad.getNode() != N0.getNode()) { in visitSIGN_EXTEND()
12145 if (NewXor.getNode() == N0.getNode()) { in visitSIGN_EXTEND()
12261 if (NarrowLoad.getNode() != N0.getNode()) { in visitZERO_EXTEND()
12511 if (NarrowLoad.getNode() != N0.getNode()) { in visitANY_EXTEND()
16109 if (Tmp.getNode() == N.getNode()) in rebuildSetCC()
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H A DLegalizeIntegerTypes.cpp278 if (Res.getNode()) in PromoteIntegerResult()
502 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
572 return DAG.getNode( in PromoteIntRes_CTLZ()
1744 if (Res.getNode() == N) in PromoteIntegerOperand()
2564 if (Lo.getNode()) in ExpandIntegerResult()
3342 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), in ExpandIntRes_CTPOP()
3615 Lo = DAG.getNode( in ExpandIntRes_LOAD()
4265 Hi = DAG.getNode( in ExpandIntRes_SIGN_EXTEND()
4820 if (!LoCmp.getNode()) in IntegerExpandSetCCOperands()
4827 if (!HiCmp.getNode()) in IntegerExpandSetCCOperands()
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H A DLegalizeTypesGeneric.cpp58 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
59 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
69 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
70 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
139 Vals.push_back(DAG.getNode( in ExpandRes_BITCAST()
230 SDValue NewVec = DAG.getNode(ISD::BITCAST, dl, in ExpandRes_EXTRACT_VECTOR_ELT()
425 SDValue NewVec = DAG.getNode(ISD::BITCAST, dl, in ExpandOp_INSERT_VECTOR_ELT()
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H A DResourcePriorityQueue.cpp74 const SDNode *ScegN = PredSU->getNode(); in numberRCValPredInSU()
112 const SDNode *ScegN = SuccSU->getNode(); in numberRCValSuccInSU()
239 if (!SU || !SU->getNode()) in isResourceAvailable()
244 if (SU->getNode()->getGluedNode()) in isResourceAvailable()
249 if (SU->getNode()->isMachineOpcode()) in isResourceAvailable()
289 if (SU->getNode() && SU->getNode()->isMachineOpcode()) { in reserveResources()
293 SU->getNode()->getMachineOpcode())); in reserveResources()
321 if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode()) in rawRegPressureDelta()
336 if (isa<ConstantSDNode>(Op.getNode())) in rawRegPressureDelta()
355 if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode()) in regPressureDelta()
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H A DTargetLowering.cpp508 return TLO.New.getNode(); in ShrinkDemandedConstant()
585 SDValue X = DAG.getNode( in ShrinkDemandedOp()
1047 DAG.getNode(AVGOpc, DL, NVT, DAG.getNode(ISD::TRUNCATE, DL, NVT, ExtOpA), in combineShiftToAVG()
6958 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || in expandMUL_LOHI()
6959 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())); in expandMUL_LOHI()
6979 if (!LL.getNode() && !RL.getNode() && in expandMUL_LOHI()
6985 if (!LL.getNode()) in expandMUL_LOHI()
7020 if (!LH.getNode() && !RH.getNode() && in expandMUL_LOHI()
7029 if (!LH.getNode()) in expandMUL_LOHI()
7269 DAG.getNode(HsOpc, DL, VT, DAG.getNode(HsOpc, DL, VT, Op0, One), HsAmt); in expandROT()
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H A DLegalizeVectorTypes.cpp195 if (R.getNode()) in ScalarizeVectorResult()
555 Src = DAG.getNode( in ScalarizeVecRes_FP_TO_XINT_SAT()
709 if (Res.getNode() == N) in ScalarizeVectorOperand()
1138 if (Lo.getNode()) in SplitVectorResult()
1366 Hi = DAG.getNode( in SplitVecRes_EXTRACT_SUBVECTOR()
1658 SDNode *LoNode = DAG.getNode(Opcode, dl, LoVTs, LoLHS, LoRHS).getNode(); in SplitVecRes_OverflowOp()
1659 SDNode *HiNode = DAG.getNode(Opcode, dl, HiVTs, HiLHS, HiRHS).getNode(); in SplitVecRes_OverflowOp()
2800 if (Res.getNode() == N) in SplitVectorOperand()
3878 if (Res.getNode()) in WidenVectorResult()
5516 if (Res.getNode() == N) in WidenVectorOperand()
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H A DLegalizeDAG.cpp585 Hi = DAG.getNode( in LegalizeStoreOps()
596 Hi = DAG.getNode( in LegalizeStoreOps()
808 Hi = DAG.getNode( in LegalizeLoadOps()
836 Hi = DAG.getNode( in LegalizeLoadOps()
1399 if (!Ch.getNode()) { in ExpandExtractFromVectorThroughStack()
1927 if (!Value1.getNode()) in ExpandBUILD_VECTOR()
2916 Op = DAG.getNode( in ExpandNode()
3523 Tmp2 = DAG.getNode( in ExpandNode()
3750 if (CC.getNode()) { in ExpandNode()
4507 Tmp1 = DAG.getNode( in PromoteNode()
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H A DLegalizeFloatTypes.cpp154 if (R.getNode()) { in SoftenFloatResult()
868 if (Res.getNode() == N) in SoftenFloatOperand()
933 if (!NewRHS.getNode()) { in SoftenFloatOp_BR_CC()
1044 if (NewRHS.getNode()) { in SoftenFloatOp_SETCC()
1280 if (Lo.getNode()) in ExpandFloatResult()
1818 if (Res.getNode() == N) in ExpandFloatOperand()
2123 if (R.getNode()) in PromoteFloatOperand()
2314 if (R.getNode()) in PromoteFloatResult()
2533 return DAG.getNode( in PromoteFloatRes_XINT_TO_FP()
2677 if (R.getNode()) in SoftPromoteHalfResult()
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/llvm-project-15.0.7/llvm/lib/BinaryFormat/
H A DMsgPackDocument.cpp80 *this = getDocument()->getNode(Val); in operator =()
84 *this = getDocument()->getNode(Val); in operator =()
88 *this = getDocument()->getNode(Val); in operator =()
92 *this = getDocument()->getNode(Val); in operator =()
96 *this = getDocument()->getNode(Val); in operator =()
153 Node = getNode(); in readFromBlob()
156 Node = getNode(Obj.Int); in readFromBlob()
159 Node = getNode(Obj.UInt); in readFromBlob()
162 Node = getNode(Obj.Bool); in readFromBlob()
165 Node = getNode(Obj.Float); in readFromBlob()
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/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DSelectionDAGAddressAnalysisTest.cpp106 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); in TEST_F()
118 Store.getNode(), NumBytes, Store.getNode(), NumBytes, *DAG, IsAlias); in TEST_F()
129 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); in TEST_F()
144 Store.getNode(), NumBytes, Store.getNode(), NumBytes, *DAG, IsAlias); in TEST_F()
175 Store0.getNode(), NumBytes0, Store1.getNode(), NumBytes1, *DAG, IsAlias); in TEST_F()
205 Store0.getNode(), NumBytes0, Store1.getNode(), NumBytes1, *DAG, IsAlias); in TEST_F()
236 Store.getNode(), NumBytes, GStore.getNode(), GNumBytes, *DAG, IsAlias); in TEST_F()
300 Store0.getNode(), NumBytes0, Store1.getNode(), NumBytes1, *DAG, IsAlias); in TEST_F()
305 Store1.getNode(), NumBytes1, Store0.getNode(), NumBytes0, *DAG, IsAlias); in TEST_F()
341 Store0.getNode(), NumBytes0, Store1.getNode(), NumBytes1, *DAG, IsAlias); in TEST_F()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp3292 if (Flag.getNode()) in LowerReturn()
5124 if (True.getNode() && False.getNode()) { in LowerSELECT()
12406 if (!IsVUZPShuffleNode(N0.getNode()) || N0.getNode() != N1.getNode() || in AddCombineToVPADD()
12444 if (!IsVUZPShuffleNode(N00.getNode()) || N00.getNode() != N10.getNode() || in AddCombineVUZPToVPADDL()
12707 if (AddcSubcOp0.getNode() == AddcSubcOp1.getNode()) in AddCombineTo64bitMLAL()
12728 if (AddeSubeOp0.getNode() == AddeSubeOp1.getNode()) in AddCombineTo64bitMLAL()
14240 if ((SRL.getOperand(0).getNode() != SHL.getOperand(0).getNode()) || in PerformORCombineToSMULWBT()
14913 Op0.getNode() == Op1.getNode() && in PerformVMOVDRRCombine()
15315 DCI.CombineTo(OtherExt.getNode(), SDValue(VMOVRRD.getNode(), 1)); in PerformExtractEltToVMOVRRD()
18016 DAG.ReplaceAllUsesWith(Int.getNode(), LoopDec.getNode()); in PerformHWLoopCombine()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp553 return DAG.getNode(ISD::SHL, dl, MVT::i32, in convertToByteIndex()
640 if (!SplatV.getNode()) in buildHvxVectorReg()
656 assert(SplatV.getNode()); in buildHvxVectorReg()
699 if (Vec.getNode() != nullptr && T.getNode() != Vec.getNode()) in buildHvxVectorReg()
1478 for (SDValue V : Op.getNode()->ops()) in LowerHvxConcatVectors()
1528 ArrayRef<SDUse> U(Op.getNode()->ops()); in LowerHvxConcatVectors()
1691 SDValue A = DAG.getNode(ISD::AND, dl, ResTy, in LowerHvxCttz()
1694 return DAG.getNode(ISD::SUB, dl, ResTy, in LowerHvxCttz()
1851 SDValue C = DAG.getNode( in LowerHvxBitcast()
2111 for (SDValue A : Op.getNode()->ops()) { in SplitHvxPairOp()
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H A DHexagonISelDAGToDAG.cpp272 SDNode *C = Ch.getNode(); in tryLoadOfLoadIntrinsic()
300 if (C->getNumOperands() < 4 || Loc.getNode() != C->getOperand(3).getNode()) in tryLoadOfLoadIntrinsic()
1079 ReplaceNode(T0.getNode(), NewShl.getNode()); in ppAddrReorderAddShl()
1155 ReplaceNode(T0.getNode(), NewShl.getNode()); in ppAddrRewriteAndSrl()
1667 assert(A.Value.getNode() && B.Value.getNode()); in Compare()
1913 if ((!isOpcodeHandled(Op0.getNode()) || RootWeights.count(Op0.getNode())) && in balanceSubTree()
1914 (!isOpcodeHandled(Op1.getNode()) || RootWeights.count(Op1.getNode()))) { in balanceSubTree()
1978 if (Child.getNode() != N && RootWeights.count(Child.getNode())) { in balanceSubTree()
2143 if (GA.Value.getNode()) in balanceSubTree()
2174 if ((RootWeights.count(V0.getNode()) && RootWeights[V0.getNode()] == -2) || in balanceSubTree()
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/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp155 SDNode *N = Res.getNode(); in lowerUINT_TO_FP()
252 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in lowerShiftLeftParts()
262 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero); in lowerShiftLeftParts()
263 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); in lowerShiftLeftParts()
315 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse); in lowerShiftRightParts()
316 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); in lowerShiftRightParts()
498 return DAG.getNode(LoongArchISD::BSTRPICK, DL, ValTy, in performSRLCombine()
624 return DAG.getNode( in performORCombine()
1009 if (Glue.getNode()) in LowerCall()
1016 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge); in LowerCall()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp548 SDValue Lo(Hi.getNode(), 1); in LowerSMUL_LOHI()
565 SDValue Lo(Hi.getNode(), 1); in LowerUMUL_LOHI()
662 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul()
670 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul()
681 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul()
722 SDValue Carry(Lo.getNode(), 1); in ExpandADDSUB()
726 SDValue Ignored(Hi.getNode(), 1); in ExpandADDSUB()
736 SDNode *Node = Op.getNode(); in LowerVAARG()
1213 if (InFlag.getNode()) in LowerCCCCallTo()
1510 if (Flag.getNode()) in LowerReturn()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3753 return DAG.getNode( in LowerVectorFP_TO_INT()
3826 return DAG.getNode( in LowerFP_TO_INT()
4054 return DAG.getNode( in LowerINT_TO_FP()
4724 return DAG.getNode( in LowerINTRINSIC_WO_CHAIN()
4730 return DAG.getNode( in LowerINTRINSIC_WO_CHAIN()
4736 return DAG.getNode( in LowerINTRINSIC_WO_CHAIN()
7080 if (Flag.getNode()) in LowerReturn()
7137 return DAG.getNode( in getAddrLarge()
7880 Val = DAG.getNode( in LowerCTPOP_PARITY()
12136 if (!Cmp.getNode()) in LowerVSETCC()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3277 if (Flag.getNode()) in LowerReturn()
4830 if (InFlag.getNode()) in LowerCall()
9037 if (!V1.getNode()) in LowerBuildVectorv4x32()
11145 assert(!VarElt.getNode() && !InsIndex.getNode() && in LowerBUILD_VECTOR()
11251 if (Op.getNode()->isOnlyUserOf(Item.getNode())) in LowerBUILD_VECTOR()
23048 Res = DAG.getNode( in LowerFP_TO_FP16()
24052 if (!Src.getNode()) in LowerAndToBT()
30754 M = DAG.getNode( in LowerRotate()
30764 M = DAG.getNode( in LowerRotate()
30774 M = DAG.getNode( in LowerRotate()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp350 if (Result.getNode()) { in LowerAsmOperandForConstraint()
591 if (Flag.getNode()) in LowerReturn()
595 return DAG.getNode(Opc, DL, MVT::Other, in LowerReturn()
695 if (StackPtr.getNode() == nullptr) in LowerCCCCallTo()
756 if (InFlag.getNode()) in LowerCCCCallTo()
951 Res = DAG.getNode(ISD::SHL, DL, VT, V, in LowerMUL()
1145 return DAG.getNode(ISD::OR, DL, MVT::i32, in LowerConstantPool()
1310 SDValue NegatedPlus32 = DAG.getNode( in LowerSRL_PARTS()
1451 if (N0.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
1454 if (N1.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1810 SDValue FpToInt = DAG.getNode( in lowerFP_TO_INT_SAT()
2411 auto InterVec = DAG.getNode( in splatPartsI64WithVL()
5754 return DAG.getNode( in lowerVECTOR_REVERSE()
6083 SDValue SplatZero = DAG.getNode( in lowerABS()
7897 SDValue Res = DAG.getNode( in combineROTR_ROTL_RORW_ROLW()
7939 return DAG.getNode( in combineGREVI_GORCI()
8745 return DAG.getNode( in performSRACombine()
11246 if (!StackPtr.getNode()) in LowerCall()
11327 if (!StackPtr.getNode()) in LowerCall()
11401 if (Glue.getNode()) in LowerCall()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp634 if (!StackPtr.getNode()) { in LowerCall()
692 if (!StackPtr.getNode()) { in LowerCall()
792 if (InFlag.getNode()) in LowerCall()
1108 if (Flag.getNode()) in LowerReturn()
1384 SDNode *N = Op.getNode(); in LowerXALUO()
1487 if (LHS.getNode()) in LowerAndToBTST()
1550 if (ISD::isNON_EXTLoad(LHS.getNode()) && !ISD::isNON_EXTLoad(RHS.getNode())) { in TranslateM68kCC()
1793 return SDValue(Op.getNode(), 1); in EmitTest()
1849 return SDValue(New.getNode(), 1); in EmitTest()
2846 if (Result.getNode()) { in LowerAsmOperandForConstraint()
[all …]

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