Lines Matching refs:getNode
412 assert((!Result.getNode() || in LowerOperation()
413 Result.getNode()->getNumValues() == 2) && in LowerOperation()
438 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
488 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
492 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
494 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
496 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
498 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
500 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
502 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
504 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
506 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
509 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); in LowerOperation()
562 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerOperation()
565 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1)); in LowerOperation()
627 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector, in vectorToVerticalVector()
631 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()
645 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
661 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
678 return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, SDLoc(GSD), ConstPtrVT, GA); in LowerGlobalAddress()
689 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT, in LowerTrig()
690 DAG.getNode(ISD::FADD, DL, VT, in LowerTrig()
691 DAG.getNode(ISD::FMUL, DL, VT, Arg, in LowerTrig()
705 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT, in LowerTrig()
706 DAG.getNode(ISD::FADD, DL, VT, FractPart, in LowerTrig()
711 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal, in LowerTrig()
718 expandShiftParts(Op.getNode(), Lo, Hi, DAG); in LowerShiftParts()
730 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO()
732 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO()
735 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi); in LowerUADDSUBO()
737 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
742 return DAG.getNode( in lowerFP_TO_UINT()
752 return DAG.getNode( in lowerFP_TO_SINT()
851 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
892 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC()
893 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC()
908 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
912 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
932 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
934 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
963 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
1025 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateTruncStore()
1030 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1041 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1045 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1050 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in lowerPrivateTruncStore()
1057 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1061 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1068 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
1071 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in lowerPrivateTruncStore()
1080 Chain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, NewStore); in lowerPrivateTruncStore()
1108 SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain); in LowerSTORE()
1128 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr, in LowerSTORE()
1145 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, PtrVT, Ptr, in LowerSTORE()
1147 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1151 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift); in LowerSTORE()
1154 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant); in LowerSTORE()
1155 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift); in LowerSTORE()
1172 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr); in LowerSTORE()
1193 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr); in LowerSTORE()
1256 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateExtLoad()
1261 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateExtLoad()
1270 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in lowerPrivateExtLoad()
1274 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateExtLoad()
1278 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt); in lowerPrivateExtLoad()
1285 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode); in lowerPrivateExtLoad()
1334 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, in LowerLOAD()
1335 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1343 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1366 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad, in LowerLOAD()
1380 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1381 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr); in LowerLOAD()
1392 return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(), in LowerBRCOND()
1551 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in CompactSwizzlableVector()
1596 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in ReorganizeVector()
1674 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, in constBufferLoad()
1676 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); in constBufferLoad()
1686 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
1710 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0), in PerformDAGCombine()
1735 return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0), in PerformDAGCombine()
1770 Ops.append(InVec.getNode()->op_begin(), in PerformDAGCombine()
1771 InVec.getNode()->op_end()); in PerformDAGCombine()
1786 DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) : in PerformDAGCombine()
1787 DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal); in PerformDAGCombine()
1811 return DAG.getNode(ISD::BITCAST, DL, N->getVTList(), in PerformDAGCombine()
1838 if (LHS.getOperand(2).getNode() != True.getNode() || in PerformDAGCombine()
1839 LHS.getOperand(3).getNode() != False.getNode() || in PerformDAGCombine()
1840 RHS.getNode() != False.getNode()) { in PerformDAGCombine()
1880 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, N->getVTList(), NewArgs); in PerformDAGCombine()
1909 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs); in PerformDAGCombine()
1937 if (!Neg.getNode()) in FoldOperand()
1943 if (!Abs.getNode()) in FoldOperand()
1952 if (!Sel.getNode()) in FoldOperand()
2042 if (!Imm.getNode()) in FoldOperand()