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Searched refs:getLocVT (Results 1 – 25 of 33) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp285 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
463 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerFormalArguments_32()
496 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
498 else if (VA.getLocVT() != MVT::i32) { in LowerFormalArguments_32()
918 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerCall_32()
933 if (VA.getLocVT() == MVT::f64) { in LowerCall_32()
984 if (VA.getLocVT() != MVT::f32) { in LowerCall_32()
1082 if (RVLocs[i].getLocVT() == MVT::v2i32) { in LowerCall_32()
1143 MVT ValTy = VA.getLocVT(); in fixupVariableFloatArgs()
1253 || VA.getLocVT() != MVT::i128) in LowerCall_64()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp311 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
314 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
317 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
523 EVT RegVT = VA.getLocVT(); in LowerCallArguments()
540 unsigned ObjSize = VA.getLocVT().getStoreSize(); in LowerCallArguments()
549 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCallArguments()
681 unsigned ObjSize = VA.getLocVT().getStoreSize(); in LowerReturn()
709 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp192 EVT LocVT = VA.getLocVT(); in convertValVTToLocVT()
225 EVT LocVT = VA.getLocVT(); in unpackFromRegLoc()
256 EVT LocVT = VA.getLocVT(); in unpackFromMemLoc()
281 assert(VA.getLocVT() == MVT::i32 && in unpack64()
346 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerFormalArguments()
449 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerReturn()
476 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
567 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerCall()
718 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
723 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerCall()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp323 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
356 InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT())); in LowerFormalArguments()
431 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
434 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
437 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
536 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp400 assert(VA.getLocVT() == MVT::i64); in LowerReturn()
467 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
471 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
480 assert(VA.getLocVT() == MVT::i64); in LowerFormalArguments()
686 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
689 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
692 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
700 assert(VA.getLocVT() == MVT::i64); in LowerCall()
815 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall()
819 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp173 assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 && in assignCustomValue()
265 assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 && in assignCustomValue()
H A DMipsISelLowering.cpp3271 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); in LowerCall()
3346 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCall()
3348 ISD::SHL, DL, VA.getLocVT(), Arg, in LowerCall()
3524 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCallResult()
3528 Shift, DL, VA.getLocVT(), Val, in LowerCallResult()
3567 MVT LocVT = VA.getLocVT(); in UnpackFromArgumentSlot()
3578 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in UnpackFromArgumentSlot()
3582 Opcode, DL, VA.getLocVT(), Val, in UnpackFromArgumentSlot()
3683 MVT RegVT = VA.getLocVT(); in LowerFormalArguments()
3716 MVT LocVT = VA.getLocVT(); in LowerFormalArguments()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp456 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
488 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; in LowerCCCArguments()
492 << EVT(VA.getLocVT()).getEVTString() << "\n"; in LowerCCCArguments()
501 VA.getLocVT(), DL, Chain, FIN, in LowerCCCArguments()
566 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
672 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
675 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
678 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp642 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
680 MVT PtrVT = VA.getLocVT(); in LowerCCCArguments()
686 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
689 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
699 VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
771 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
838 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
841 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
844 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp3313 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3322 ArgVT = VA.getLocVT(); in fastLowerCall()
3326 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3342 ArgVT = VA.getLocVT(); in fastLowerCall()
3346 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3348 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3351 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3354 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3358 ArgVT = VA.getLocVT(); in fastLowerCall()
3362 ArgReg = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, ArgReg); in fastLowerCall()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1148 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1151 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1154 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1299 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
1319 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
1322 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
1333 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
1476 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; in LowerReturn()
1504 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp319 if (VA.getLocVT().getSizeInBits() > Arg.getValueType().getSizeInBits()) { in MatchingStackOffset()
393 ValVT = VA.getLocVT(); in LowerMemArgument()
596 EVT RegVT = VA.getLocVT(); in LowerCall()
685 uint32_t OpSize = (VA.getLocVT().getSizeInBits() + 7) / 8; in LowerCall()
850 EVT CopyVT = VA.getLocVT(); in LowerCallResult()
899 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
1044 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1046 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1051 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1053 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy); in LowerReturn()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp118 assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size"); in assignValueToReg()
289 uint64_t LocSize = VA.getLocVT().getFixedSizeInBits(); in assignValueToReg()
H A DARMCallingConv.cpp178 assert(PendingMembers[0].getLocVT() == LocVT); in CC_ARM_AAPCS_Custom_Aggregate()
H A DARMFastISel.cpp1903 if (VA.getLocVT() != MVT::f64 || in ProcessCallArgs()
1953 MVT DestVT = VA.getLocVT(); in ProcessCallArgs()
1962 MVT DestVT = VA.getLocVT(); in ProcessCallArgs()
1969 unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg); in ProcessCallArgs()
1972 ArgVT = VA.getLocVT(); in ProcessCallArgs()
1985 assert(VA.getLocVT() == MVT::f64 && in ProcessCallArgs()
H A DARMISelLowering.cpp2193 (VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2f64)) { in LowerCallResult()
2208 if (VA.getLocVT() == MVT::v2f64) { in LowerCallResult()
2266 int Size = VA.getLocVT().getFixedSizeInBits() / 8; in computeAddrForCallArg()
2500 auto LocBits = VA.getLocVT().getSizeInBits(); in LowerCall()
2511 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) { in LowerCall()
2538 assert(VA.getLocVT() == MVT::i32 && in LowerCall()
3057 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization()
3220 auto LocBits = VA.getLocVT().getSizeInBits(); in LowerReturn()
3231 (VA.getLocVT() == MVT::v2f64 || VA.getLocVT() == MVT::f64)) { in LowerReturn()
3232 if (VA.getLocVT() == MVT::v2f64) { in LowerReturn()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp234 Val = DAG.getBitcast(VA.getLocVT(), Val); in LowerReturn()
237 Val = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
240 Val = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
243 Val = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
483 Arg = DAG.getBitcast(VA.getLocVT(), Arg); in LowerCall()
486 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
489 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
492 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
839 MVT RegVT = VA.getLocVT(); in LowerFormalArguments()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp74 : LLT(VA.getLocVT()); in getStackValueStoreTypeHack()
171 LLT LocTy(VA.getLocVT()); in assignValueToAddress()
311 MVT LocVT = VA.getLocVT(); in assignValueToAddress()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp669 const MVT LocVT = VA.getLocVT(); in handleAssignments()
1113 LLT LocTy{VA.getLocVT()}; in extendRegister()
1205 const MVT LocVT = VA.getLocVT(); in assignValueToReg()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp882 EVT LocVT = VA.getLocVT(); in unpackFromRegLoc()
1033 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
1078 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h151 MVT getLocVT() const { return LocVT; } in getLocVT() function
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp36 if (VA.getLocVT().getSizeInBits() < 32) { in extendRegisterMin32()
110 if (VA.getLocVT().getSizeInBits() < 32) { in assignValueToReg()
118 buildExtensionHint(VA, Copy.getReg(0), LLT(VA.getLocVT())); in assignValueToReg()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1373 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1384 assert(VA.getLocVT() == MVT::i64); in convertLocVTToValVT()
1406 assert(VA.getLocVT() == MVT::i64 || VA.getLocVT() == MVT::i128); in convertValVTToLocVT()
1411 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i64) in convertValVTToLocVT()
1415 : VA.getLocVT(); in convertValVTToLocVT()
1506 EVT LocVT = VA.getLocVT(); in LowerFormalArguments()
1566 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32) in LowerFormalArguments()
1763 if (VA.getLocVT() == MVT::i128) in LowerCall()
1777 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32) in LowerCall()
1874 VA.getLocVT(), Glue); in LowerCall()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1236 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
1280 EVT LocVT = VA.getLocVT(); in LowerFormalArguments()
1369 EVT RegVT = VA.getLocVT(); in LowerCall()
1564 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1442 MVT DestVT = VA.getLocVT(); in processCallArgs()
1454 MVT DestVT = VA.getLocVT(); in processCallArgs()
1755 MVT DestVT = VA.getLocVT(); in SelectRet()

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