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Searched refs:getLocReg (Results 1 – 25 of 32) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp115 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
165 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
166 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
170 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
171 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
286 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
333 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
334 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
H A DARMFastISel.cpp1982 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1998 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1999 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2045 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2046 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2048 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2049 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2066 ResultReg).addReg(RVLocs[0].getLocReg()); in FinishCall()
2067 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2145 Register DstReg = VA.getLocReg(); in SelectRet()
[all …]
H A DARMISelLowering.cpp2546 CSInfo.emplace_back(VA.getLocReg(), i); in LowerCall()
2547 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
3240 DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
3246 DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
3260 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
3263 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
3265 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
3268 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); in LowerReturn()
4291 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in GetF64FormalArgument()
4305 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); in GetF64FormalArgument()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp177 auto CopyLo = MIRBuilder.buildCopy(LLT::scalar(32), VALo.getLocReg()); in assignCustomValue()
178 auto CopyHi = MIRBuilder.buildCopy(LLT::scalar(32), VAHi.getLocReg()); in assignCustomValue()
186 markPhysRegUsed(VALo.getLocReg()); in assignCustomValue()
187 markPhysRegUsed(VAHi.getLocReg()); in assignCustomValue()
283 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
284 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
288 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
289 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
H A DMipsFastISel.cpp1225 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
1226 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
1296 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1297 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
1722 Register DestReg = VA.getLocReg(); in selectRet()
1763 RetRegs.push_back(VA.getLocReg()); in selectRet()
H A DMipsISelLowering.cpp3313 Register LocRegLo = VA.getLocReg(); in LowerCall()
3314 Register LocRegHigh = ArgLocs[++i].getLocReg(); in LowerCall()
3355 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
3359 if (Mips::AFGR64RegClass.contains(VA.getLocReg())) in LowerCall()
3365 CSInfo.emplace_back(VA.getLocReg(), i); in LowerCall()
3517 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
3684 Register ArgReg = VA.getLocReg(); in LowerFormalArguments()
3706 addLiveIn(DAG.getMachineFunction(), NextVA.getLocReg(), RC); in LowerFormalArguments()
3883 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); in LowerReturn()
3887 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp246 RegInfo.addLiveIn(VA.getLocReg(), VReg); in unpackFromRegLoc()
299 RegInfo.addLiveIn(VA.getLocReg(), LoVReg); in unpack64()
302 if (VA.getLocReg() == CSKY::R3) { in unpack64()
311 RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg); in unpack64()
459 Register RegLo = VA.getLocReg(); in LowerReturn()
472 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); in LowerReturn()
476 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
576 Register RegLo = VA.getLocReg(); in LowerCall()
604 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
718 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp300 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
390 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
466 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
479 Register loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
494 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments_32()
645 Register VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64()
989 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32()
1158 unsigned Offset = argSize * (VA.getLocReg() - firstReg); in fixupVariableFloatArgs()
1262 unsigned Offset = 8 * (VA.getLocReg() - SP::I0); in LowerCall_64()
1294 ArgLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerCall_64()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCallingConvLower.cpp74 if (ValAssign.isRegLoc() && TRI.regsOverlap(ValAssign.getLocReg(), Reg)) in IsShadowAllocatedReg()
227 Regs.push_back(MCPhysReg(Locs[I].getLocReg())); in getRemainingRegParmsForType()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp335 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
443 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
531 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
536 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
569 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), in LowerCallResult()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp324 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
419 DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), Glue); in lowerCallResult()
532 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCallArguments()
704 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
709 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp783 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); in handleAssignments()
786 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); in handleAssignments()
968 MCRegister PhysReg = ArgLoc.getLocReg(); in parametersInCSRMatch()
1049 if (Loc1.getLocReg() != Loc2.getLocReg()) in resultsCompatible()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp885 RegInfo.addLiveIn(VA.getLocReg(), VReg); in unpackFromRegLoc()
969 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
1033 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
1074 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
1078 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp460 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
562 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
566 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
691 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
792 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(), in LowerCallResult()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp654 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
765 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
771 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
851 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
949 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h148 Register getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg() function
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp1235 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in X86SelectRet()
1265 Register DstReg = VA.getLocReg(); in X86SelectRet()
1274 RetRegs.push_back(VA.getLocReg()); in X86SelectRet()
3385 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in fastLowerCall()
3386 OutRegs.push_back(VA.getLocReg()); in fastLowerCall()
3536 Register SrcReg = VA.getLocReg(); in fastLowerCall()
3555 InRegs.push_back(VA.getLocReg()); in fastLowerCall()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1246 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
1401 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1504 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(), in LowerCallResult()
1560 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
1564 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1067 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), in LowerCallResult()
1161 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
1311 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1499 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
1504 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp631 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
853 Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), CopyVT, InFlag) in LowerCallResult()
906 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
1055 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), ValToCopy, Flag); in LowerReturn()
1057 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
1282 Register Reg = VA.getLocReg(); in IsEligibleForTailCallOptimization()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp247 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Val, Flag); in LowerReturn()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
375 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
389 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
521 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
864 MRI.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
865 HFL.FirstVarArgSavedReg = NextSingleReg(*RC, VA.getLocReg()); in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp414 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn()
418 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
460 MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT())); in LowerFormalArguments()
713 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
794 Register Reg = VA.getLocReg(); in LowerCall()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4112 Register RegLo = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
4113 Register RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC); in LowerFormalArguments_32SVR4()
4121 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
5894 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32SVR4()
7002 MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_AIX()
7079 const MCPhysReg ArgReg = VA.getLocReg(); in LowerFormalArguments_AIX()
7117 HandleRegLoc(VA.getLocReg(), Offset); in LowerFormalArguments_AIX()
7125 HandleRegLoc(RL.getLocReg(), Offset); in LowerFormalArguments_AIX()
7144 MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_AIX()
7393 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_AIX()
[all …]
H A DPPCFastISel.cpp1517 unsigned SourcePhysReg = VA.getLocReg(); in finishCall()
1724 Register RetReg = VA.getLocReg(); in SelectRet()
1748 RetRegs.push_back(VA.getLocReg()); in SelectRet()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3045 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
3046 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
3110 .addReg(RVLocs[0].getLocReg()); in finishCall()
3111 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
3814 Register DestReg = VA.getLocReg(); in selectRet()
3857 RetRegs.push_back(VA.getLocReg()); in selectRet()

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