| /llvm-project-15.0.7/llvm/unittests/CodeGen/ |
| H A D | ScalableVectorMVTsTest.cpp | 155 EXPECT_LT(v2i32.getFixedSizeInBits(), v2i64.getFixedSizeInBits()); in TEST()
156 EXPECT_LE(v4i32.getFixedSizeInBits(), v2i64.getFixedSizeInBits()); in TEST()
157 EXPECT_GT(v4i32.getFixedSizeInBits(), v2i32.getFixedSizeInBits()); in TEST()
158 EXPECT_GE(v2i64.getFixedSizeInBits(), v4i32.getFixedSizeInBits()); in TEST()
166 EXPECT_EQ(v4i32.getFixedSizeInBits(), 128U); in TEST()
167 EXPECT_EQ(v2i64.getFixedSizeInBits(), 128U); in TEST()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 288 uint64_t ValSize = VA.getValVT().getFixedSizeInBits(); in assignValueToReg()
289 uint64_t LocSize = VA.getLocVT().getFixedSizeInBits(); in assignValueToReg()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TypePromotion.cpp | 931 if (RegisterBitWidth < PromotedVT.getFixedSizeInBits()) { in runOnFunction()
937 MadeChange |= TryToPromote(I, PromotedVT.getFixedSizeInBits()); in runOnFunction()
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| H A D | TargetLoweringBase.cpp | 772 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions()
1415 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() && in computeRegisterProperties()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.h | 348 uint64_t getFixedSizeInBits() const { in getFixedSizeInBits() function
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| H A D | SelectionDAGNodes.h | 197 return getValueType().getScalarType().getFixedSizeInBits();
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | IntrinsicEmitter.cpp | 265 unsigned BitWidth = MVT(VT).getFixedSizeInBits(); in EncodeFixedValueType()
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| H A D | CodeGenDAGPatterns.cpp | 2502 unsigned Size = MVT(VT).getFixedSizeInBits(); in ApplyTypeConstraints()
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 1404 return (VT1.getFixedSizeInBits() > VT2.getFixedSizeInBits()); in isTruncateFree()
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 216 switch (PowerOf2Ceil(VT.getFixedSizeInBits())) { in PromoteScalarIntegerPTX()
2620 Ins[InsIdx].VT.getFixedSizeInBits() > in LowerFormalArguments()
2621 LoadVT.getFixedSizeInBits()) { in LowerFormalArguments()
4726 if (OrigVT.getFixedSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
4732 if (OrigVT.getFixedSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2194 size_t DestLaneSize = VecT.getVectorElementType().getFixedSizeInBits() / 8; in LowerBUILD_VECTOR()
2202 Src1.getValueType().getVectorElementType().getFixedSizeInBits() / 8; in LowerBUILD_VECTOR()
2209 Src2.getValueType().getVectorElementType().getFixedSizeInBits() / 8; in LowerBUILD_VECTOR()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3758 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorFP_TO_INT()
3759 uint64_t InVTSize = InVT.getFixedSizeInBits(); in LowerVectorFP_TO_INT()
3994 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorINT_TO_FP()
3995 uint64_t InVTSize = InVT.getFixedSizeInBits(); in LowerVectorINT_TO_FP()
5659 if (VT.getFixedSizeInBits() <= 128) in useSVEForFixedLengthVectorVT()
9070 if (VT.getFixedSizeInBits() == 64) in getRegForInlineAsmConstraint()
9081 uint64_t VTSize = VT.getFixedSizeInBits(); in getRegForInlineAsmConstraint()
9496 uint64_t VTSize = VT.getFixedSizeInBits(); in ReconstructShuffle()
9583 SrcEltTy.getFixedSizeInBits() / SmallestEltTy.getFixedSizeInBits(); in ReconstructShuffle()
12575 uint64_t NumBits1 = VT1.getFixedSizeInBits(); in isTruncateFree()
[all …]
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| H A D | AArch64TargetTransformInfo.cpp | 1913 if (DstVT.getFixedSizeInBits() < SrcVT.getFixedSizeInBits()) in getExtractWithExtendCost()
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| H A D | AArch64ISelDAGToDAG.cpp | 250 /* High */ EltVT.getFixedSizeInBits(), in SelectSVEShiftSplatImmR()
3226 .trunc(VT.getFixedSizeInBits()) in SelectSVEAddSubImm()
3266 .trunc(VT.getFixedSizeInBits()) in SelectSVECpyDupImm()
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| /llvm-project-15.0.7/llvm/include/llvm/Support/ |
| H A D | MachineValueType.h | 1087 uint64_t getFixedSizeInBits() const { in getFixedSizeInBits() function
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 8615 unsigned NumBits = NewStoredVT.getFixedSizeInBits(); in expandUnalignedStore()
8673 APInt(AddrVT.getFixedSizeInBits(), in IncrementMemoryAddress()
8699 DAG.getVScale(dl, IdxVT, APInt(IdxVT.getFixedSizeInBits(), NElts)); in clampDynamicVectorIndex()
8735 unsigned EltSize = EltVT.getFixedSizeInBits() / 8; // FIXME: should be ABI size. in getVectorSubVecPointer()
8736 assert(EltSize * 8 == EltVT.getFixedSizeInBits() && in getVectorSubVecPointer()
9369 unsigned LoSize = VT.getFixedSizeInBits(); in expandMULO()
9668 APInt(PtrVT.getFixedSizeInBits(), VT.getStoreSize().getKnownMinSize())); in expandVectorSplice()
9691 APInt(PtrVT.getFixedSizeInBits(), VT.getStoreSize().getKnownMinSize())); in expandVectorSplice()
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| H A D | LegalizeVectorTypes.cpp | 1738 EltVT.getFixedSizeInBits() / 8)); in SplitVecRes_INSERT_VECTOR_ELT()
3088 commonAlignment(SmallestAlign, EltVT.getFixedSizeInBits() / 8)); in SplitVecOp_EXTRACT_VECTOR_ELT()
5739 unsigned EltSize = EltVT.getFixedSizeInBits(); in WidenVecOp_BITCAST()
6278 if (RetVT.getFixedSizeInBits() < MemVTWidth || MemVT == WidenVT) in findMemType()
6570 unsigned ValEltWidth = ValEltVT.getFixedSizeInBits(); in GenWidenVectorStores()
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| H A D | SelectionDAGBuilder.cpp | 435 const uint64_t ValueSize = ValueVT.getFixedSizeInBits(); in getCopyFromPartsVector()
685 uint64_t ValueSize = ValueVT.getFixedSizeInBits(); in getCopyToPartsVector()
686 assert(PartVT.getFixedSizeInBits() > ValueSize && in getCopyToPartsVector()
6627 if (PtrTy.getFixedSizeInBits() < ResTy.getFixedSizeInBits()) in visitIntrinsicCall()
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| H A D | DAGCombiner.cpp | 6501 LHS.getOperand(0).getValueType().getFixedSizeInBits())) in visitAND()
16737 DAG.getConstant(APInt::getLowBitsSet(STType.getFixedSizeInBits(), in ForwardStoreValueToDirectLoad()
19136 unsigned STBitSize = ST->getMemoryVT().getFixedSizeInBits(); in visitSTORE()
19137 unsigned ChainBitSize = ST1->getMemoryVT().getFixedSizeInBits(); in visitSTORE()
20282 uint64_t VTSize = VT.getFixedSizeInBits(); in createBuildVecShuffle()
20283 uint64_t InVT1Size = InVT1.getFixedSizeInBits(); in createBuildVecShuffle()
20284 uint64_t InVT2Size = InVT2.getFixedSizeInBits(); in createBuildVecShuffle()
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 2652 std::min(PtrVT.getFixedSizeInBits(), VT.getFixedSizeInBits()) / 8); in LowerVAARG()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 6654 if (ValVT.getFixedSizeInBits() < RegVT.getFixedSizeInBits()) in CC_AIX()
6843 assert(ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits()); in truncateScalarIntegerArg()
7149 (ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits())) { in LowerFormalArguments_AIX()
7470 else if (Arg.getValueType().getFixedSizeInBits() < in LowerCall_AIX()
7471 LocVT.getFixedSizeInBits()) in LowerCall_AIX()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1606 if (VT.getFixedSizeInBits() > 1024 * 8) in useRVVForFixedLengthVectorVT()
3719 LLT(Ty.getSimpleVT()), Align(Ty.getFixedSizeInBits() / 8)); in getAddr()
3795 LLT(Ty.getSimpleVT()), Align(Ty.getFixedSizeInBits() / 8)); in getStaticTLSAddr()
12422 unsigned Count = PartVTBitSize / ValueEltVT.getFixedSizeInBits(); in splitValueIntoRegisterParts()
12474 unsigned Count = PartVTBitSize / ValueEltVT.getFixedSizeInBits(); in joinRegisterPartsIntoValue()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3199 if (VT.getFixedSizeInBits() <= EltVT.getFixedSizeInBits()) { in performTruncateCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 124 VT.getFixedSizeInBits() < RegisterVT.getFixedSizeInBits() in getVectorTypeBreakdownForCallingConv()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 368 int ElemWidth = ElemTy.getFixedSizeInBits(); in initializeHVXLowering()
|