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Searched refs:getExtensionType (Results 1 – 25 of 45) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h2339 ISD::LoadExtType getExtensionType() const {
2474 ISD::LoadExtType getExtensionType() const {
2503 ISD::LoadExtType getExtensionType() const {
2646 ISD::LoadExtType getExtensionType() const {
2835 ISD::LoadExtType getExtensionType() const {
3027 return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD &&
3034 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
3040 cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
3046 cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
3052 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
/llvm-project-15.0.7/llvm/lib/Support/
H A DRISCVISAInfo.cpp186 static StringRef getExtensionType(StringRef Ext) { in getExtensionType() function
644 StringRef Type = getExtensionType(Ext); in parseArchString()
689 StringRef Desc = getExtensionTypeDesc(getExtensionType(Ext)); in parseArchString()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td832 // cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
834 // cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
1719 return MGN->getExtensionType() == ISD::EXTLOAD &&
1726 return MGN->getExtensionType() == ISD::EXTLOAD &&
1733 return MGN->getExtensionType() == ISD::EXTLOAD &&
1742 return MGN->getExtensionType() == ISD::SEXTLOAD &&
1749 return MGN->getExtensionType() == ISD::SEXTLOAD &&
1756 return MGN->getExtensionType() == ISD::SEXTLOAD &&
1765 return MGN->getExtensionType() == ISD::ZEXTLOAD &&
1772 return MGN->getExtensionType() == ISD::ZEXTLOAD &&
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/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp704 switch (LD->getExtensionType()) { in print_details()
736 switch (MLd->getExtensionType()) { in print_details()
773 switch (MGather->getExtensionType()) { in print_details()
H A DDAGCombiner.cpp6320 switch (Load->getExtensionType()) { in visitAND()
6335 if (Load->getExtensionType() == ISD::EXTLOAD) { in visitAND()
7854 return L->getExtensionType() == ISD::ZEXTLOAD in calculateByteProvider()
12787 if ((LN->getExtensionType() == ISD::SEXTLOAD || in reduceLoadWidth()
12788 LN->getExtensionType() == ISD::ZEXTLOAD) && in reduceLoadWidth()
12789 LN->getExtensionType() != ExtType) in reduceLoadWidth()
12844 if (LN->getExtensionType() == ISD::SEXTLOAD) in reduceLoadWidth()
16634 switch (LD->getExtensionType()) { in extendLoadedValueToExtension()
23757 (LLD->getExtensionType() != RLD->getExtensionType() && in SimplifySelectOps()
23759 LLD->getExtensionType() != ISD::EXTLOAD && in SimplifySelectOps()
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H A DLegalizeFloatTypes.cpp706 if (L->getExtensionType() == ISD::NON_EXTLOAD) { in SoftenFloatRes_LOAD()
707 NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), NVT, dl, in SoftenFloatRes_LOAD()
1648 Hi = DAG.getExtLoad(LD->getExtensionType(), dl, NVT, Chain, Ptr, in ExpandFloatRes_LOAD()
2493 L->getAddressingMode(), L->getExtensionType(), IVT, SDLoc(N), in PromoteFloatRes_LOAD()
2796 assert(L->getExtensionType() == ISD::NON_EXTLOAD && "Unexpected extension!"); in SoftPromoteHalfRes_LOAD()
2798 DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), MVT::i16, in SoftPromoteHalfRes_LOAD()
H A DLegalizeVectorTypes.cpp370 ISD::UNINDEXED, N->getExtensionType(), in ScalarizeVecRes_LOAD()
1805 ISD::LoadExtType ExtType = LD->getExtensionType(); in SplitVecRes_LOAD()
1851 ISD::LoadExtType ExtType = LD->getExtensionType(); in SplitVecRes_VP_LOAD()
1938 ISD::LoadExtType ExtType = MLD->getExtensionType(); in SplitVecRes_MLOAD()
2063 ISD::LoadExtType ExtType = MGT->getExtensionType(); in SplitVecRes_Gather()
4817 ISD::LoadExtType ExtType = LD->getExtensionType(); in WidenVecRes_LOAD()
4895 ISD::LoadExtType ExtType = N->getExtensionType(); in WidenVecRes_VP_LOAD()
4924 ISD::LoadExtType ExtType = N->getExtensionType(); in WidenVecRes_MLOAD()
4973 N->getIndexType(), N->getExtensionType()); in WidenVecRes_MGATHER()
5968 MG->getExtensionType()); in WidenVecOp_MGATHER()
H A DLegalizeVectorOps.cpp270 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp128 if ((LD->getExtensionType() != ISD::NON_EXTLOAD) || in selectIndexedLoad()
171 if (LD->getExtensionType() != ISD::NON_EXTLOAD || in selectIndexedProgMemLoad()
H A DAVRISelLowering.cpp941 if (LD->getExtensionType() != ISD::NON_EXTLOAD) in getPreIndexedAddressParts()
996 if (LD->getExtensionType() != ISD::NON_EXTLOAD) in getPostIndexedAddressParts()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp299 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD) in isValidIndexedLoad()
H A DMSP430ISelLowering.cpp1345 if (LD->getExtensionType() != ISD::NON_EXTLOAD) in getPostIndexedAddressParts()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1246 ISD::LoadExtType ExtType = Load->getExtensionType(); in lowerPrivateExtLoad()
1302 ISD::LoadExtType ExtType = LoadNode->getExtensionType(); in LowerLOAD()
1325 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) || in LowerLOAD()
1326 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) { in LowerLOAD()
1361 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) { in LowerLOAD()
H A DR600Instructions.td306 return L->getExtensionType() == ISD::ZEXTLOAD ||
307 L->getExtensionType() == ISD::EXTLOAD;
H A DAMDGPUISelDAGToDAG.cpp238 LoadOp = LdHi->getExtensionType() == ISD::SEXTLOAD ? in matchLoadD16FromBuildVector()
266 LoadOp = LdLo->getExtensionType() == ISD::SEXTLOAD ? in matchLoadD16FromBuildVector()
H A DSIISelLowering.cpp8562 assert((!MemVT.isVector() || Ld->getExtensionType() == ISD::NON_EXTLOAD) && in widenLoad()
8575 assert(Ld->getExtensionType() == ISD::NON_EXTLOAD && in widenLoad()
8581 if (Ld->getExtensionType() == ISD::SEXTLOAD) { in widenLoad()
8584 } else if (Ld->getExtensionType() == ISD::ZEXTLOAD || in widenLoad()
8585 Ld->getExtensionType() == ISD::NON_EXTLOAD) { in widenLoad()
8588 assert(Ld->getExtensionType() == ISD::EXTLOAD); in widenLoad()
8598 Cvt = getLoadExtOrTrunc(DAG, Ld->getExtensionType(), Cvt, SL, IntVT); in widenLoad()
8610 ISD::LoadExtType ExtType = Load->getExtensionType(); in LowerLOAD()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td515 unsigned Type = cast<LoadSDNode>(N)->getExtensionType();
530 unsigned Type = cast<LoadSDNode>(N)->getExtensionType();
545 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD;
H A DSystemZISelDAGToDAG.cpp999 (Load->getExtensionType() == ISD::EXTLOAD || in tryRISBGZero()
1000 Load->getExtensionType() == ISD::ZEXTLOAD) && in tryRISBGZero()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp76 ISD::LoadExtType ExtType = LD->getExtensionType(); in SelectIndexedLoad()
295 if (N->getExtensionType() != IntExt) in tryLoadOfLoadIntrinsic()
1479 if (L->getExtensionType() != ISD::SEXTLOAD) in DetectUseSxtw()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrInfo.td521 ISD::LoadExtType ExtType = LD->getExtensionType();
531 ISD::LoadExtType ExtType = LD->getExtensionType();
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1609 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD) in tryARMIndexedLoad()
1613 if (LD->getExtensionType() == ISD::SEXTLOAD) { in tryARMIndexedLoad()
1665 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD || in tryT1IndexedLoad()
1695 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD; in tryT2IndexedLoad()
1760 isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD; in tryMVEIndexedLoad()
1776 isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD; in tryMVEIndexedLoad()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp899 if (PlainLoad && (PlainLoad->getExtensionType() == ISD::SEXTLOAD)) in tryLoad()
1677 bool IsSigned = LdNode->getExtensionType() == ISD::SEXTLOAD; in tryLDGLDU()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3054 LD->getExtensionType() == ISD::SEXTLOAD && in getPreIndexedAddressParts()
8280 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() || in canReuseLoadAddress()
13996 return LD->getExtensionType() == ISD::EXTLOAD && in isFPExtLoad()
14114 IsRoundOfExtLoad = LD->getExtensionType() == ISD::EXTLOAD; in combineBVOfConsecutiveLoads()
14137 if (IsRoundOfExtLoad && LD2->getExtensionType() != ISD::EXTLOAD) in combineBVOfConsecutiveLoads()
14345 (LD->getExtensionType() != ISD::ZEXTLOAD && in combineBVZEXTLOAD()
14346 LD->getExtensionType() != ISD::EXTLOAD)) in combineBVZEXTLOAD()
15265 if (LD->getExtensionType() != ISD::NON_EXTLOAD || in PerformDAGCombine()
16626 (LD->getExtensionType() == ISD::NON_EXTLOAD || in isZExtFree()
16627 LD->getExtensionType() == ISD::ZEXTLOAD)) in isZExtFree()
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H A DPPCISelDAGToDAG.cpp3000 if (InputLoad && InputLoad->getExtensionType() == ISD::SEXTLOAD) in signExtendInputIfNeeded()
3039 if (InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD) in zeroExtendInputIfNeeded()
5285 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select()
5322 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3359 cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD && in getAArch64Cmp()
4933 ISD::LoadExtType ExtType = MGT->getExtensionType(); in LowerMGATHER()
5121 LoadNode->getExtensionType()); in LowerMLOAD()
5297 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) in LowerLOAD()
5299 else if (LoadNode->getExtensionType() == ISD::ZEXTLOAD || in LowerLOAD()
5300 LoadNode->getExtensionType() == ISD::EXTLOAD) in LowerLOAD()
15230 LD->getExtensionType() == ISD::NON_EXTLOAD; in performConcatVectorsCombine()
17782 Ops, MGT->getMemOperand(), IndexType, MGT->getExtensionType()); in performMaskedGatherScatterCombine()
17942 ExtType = LoadNode->getExtensionType(); in checkValueWidth()
21001 Load->getAddressingMode(), Load->getExtensionType()); in LowerFixedLengthVectorLoadToSVE()
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