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Searched refs:VecSize (Results 1 – 25 of 33) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ShuffleDecode.cpp479 unsigned VecSize = NumElts * ScalarBits; in DecodeVPERMILPMask() local
480 unsigned NumLanes = VecSize / 128; in DecodeVPERMILPMask()
482 assert((VecSize == 128 || VecSize == 256 || VecSize == 512) && in DecodeVPERMILPMask()
501 unsigned VecSize = NumElts * ScalarBits; in DecodeVPERMIL2PMask() local
502 unsigned NumLanes = VecSize / 128; in DecodeVPERMIL2PMask()
504 assert((VecSize == 128 || VecSize == 256) && "Unexpected vector size"); in DecodeVPERMIL2PMask()
/llvm-project-15.0.7/llvm/test/Linker/
H A Dtestlink.ll14 ; CHECK: %VecSize = type { <5 x i32> }
15 ; CHECK: %VecSize.{{[0-9]}} = type { <10 x i32> }
16 %VecSize = type { <5 x i32> }
109 define void @VecSizeCrash(%VecSize) {
/llvm-project-15.0.7/llvm/test/Linker/Inputs/
H A Dtestlink.ll7 %VecSize = type { <10 x i32> }
56 define void @VecSizeCrash1(%VecSize) {
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonVExtract.cpp161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction() local
171 SR == 0 ? 0 : VecSize/2); in runOnMachineFunction()
H A DHexagonPatternsHVX.td85 int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);
86 assert(isPowerOf2_32(VecSize));
87 if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0)
89 int32_t L = Log2_32(VecSize);
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp1294 if (VecSize <= 32) // 4 bytes in getIndirectGPRIDXPseudo()
1314 if (VecSize <= 32) // 4 bytes in getIndirectGPRIDXPseudo()
1316 if (VecSize <= 64) // 8 bytes in getIndirectGPRIDXPseudo()
1318 if (VecSize <= 96) // 12 bytes in getIndirectGPRIDXPseudo()
1335 if (VecSize <= 32) // 4 bytes in getIndirectVGPRWriteMovRelPseudoOpc()
1337 if (VecSize <= 64) // 8 bytes in getIndirectVGPRWriteMovRelPseudoOpc()
1339 if (VecSize <= 96) // 12 bytes in getIndirectVGPRWriteMovRelPseudoOpc()
1356 if (VecSize <= 32) // 4 bytes in getIndirectSGPRWriteMovRelPseudo32()
1358 if (VecSize <= 64) // 8 bytes in getIndirectSGPRWriteMovRelPseudo32()
1360 if (VecSize <= 96) // 12 bytes in getIndirectSGPRWriteMovRelPseudo32()
[all …]
H A DAMDGPUISelDAGToDAG.cpp2730 unsigned VecSize = Src.getValueSizeInBits(); in SelectVOP3PMods() local
2734 if (Lo.getValueSizeInBits() > VecSize) { in SelectVOP3PMods()
2736 (VecSize > 32) ? AMDGPU::sub0_sub1 : AMDGPU::sub0, SDLoc(In), in SelectVOP3PMods()
2737 MVT::getIntegerVT(VecSize), Lo); in SelectVOP3PMods()
2740 if (Hi.getValueSizeInBits() > VecSize) { in SelectVOP3PMods()
2743 MVT::getIntegerVT(VecSize), Hi); in SelectVOP3PMods()
2746 assert(Lo.getValueSizeInBits() <= VecSize && in SelectVOP3PMods()
2747 Hi.getValueSizeInBits() <= VecSize); in SelectVOP3PMods()
2753 if (VecSize == 32 || VecSize == Lo.getValueSizeInBits()) { in SelectVOP3PMods()
2756 assert(Lo.getValueSizeInBits() == 32 && VecSize == 64); in SelectVOP3PMods()
[all …]
H A DSIInstrInfo.h255 const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
259 const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
H A DSIISelLowering.cpp5678 unsigned VecSize = VecVT.getSizeInBits(); in lowerINSERT_VECTOR_ELT() local
5722 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerINSERT_VECTOR_ELT()
5770 if (VecSize == 128 || VecSize == 256) { in lowerEXTRACT_VECTOR_ELT()
5775 if (VecSize == 128) { in lowerEXTRACT_VECTOR_ELT()
5784 assert(VecSize == 256); in lowerEXTRACT_VECTOR_ELT()
5808 assert(VecSize <= 64); in lowerEXTRACT_VECTOR_ELT()
5810 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerEXTRACT_VECTOR_ELT()
10591 unsigned VecSize = EltSize * NumElem; in shouldExpandVectorDynExt() local
10594 if (VecSize <= 64 && EltSize < 32) in shouldExpandVectorDynExt()
10721 VecSize > 32 && in performExtractVectorEltCombine()
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H A DAMDGPURegisterBankInfo.cpp4063 unsigned VecSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); in getInstrMapping() local
4069 OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, VecSize); in getInstrMapping()
4070 OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, VecSize); in getInstrMapping()
H A DSIInstructions.td1981 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> {
1985 (!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $src, $idx, imm:$offset)
1991 (!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $src, $idx, imm:$offset, $val)
H A DAMDGPUInstructionSelector.cpp2768 unsigned VecSize = VecTy.getSizeInBits(); in selectG_INSERT_VECTOR_ELT() local
2811 VecSize, ValSize, VecRB->getID() == AMDGPU::SGPRRegBankID); in selectG_INSERT_VECTOR_ELT()
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h421 VecSize = 3 << VecSizeShift, enumerator
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp2097 unsigned VecSize; in tryLoadParam() local
2102 VecSize = 1; in tryLoadParam()
2105 VecSize = 2; in tryLoadParam()
2108 VecSize = 4; in tryLoadParam()
2117 switch (VecSize) { in tryLoadParam()
2147 if (VecSize == 1) { in tryLoadParam()
2149 } else if (VecSize == 2) { in tryLoadParam()
H A DNVPTXReplaceImageHandles.cpp1749 unsigned VecSize = in processInstr() local
1753 MachineOperand &SurfHandle = MI.getOperand(VecSize); in processInstr()
H A DNVPTXAsmPrinter.cpp172 unsigned VecSize = in lowerImageHandleOperand() local
176 if (OpNo == VecSize && MO.isImm()) { in lowerImageHandleOperand()
/llvm-project-15.0.7/clang/lib/Sema/
H A DSemaType.cpp2634 Optional<llvm::APSInt> VecSize = SizeExpr->getIntegerConstantExpr(Context); in BuildVectorType() local
2635 if (!VecSize) { in BuildVectorType()
2647 if (!VecSize->isIntN(61)) { in BuildVectorType()
2653 uint64_t VectorSizeBits = VecSize->getZExtValue() * 8; in BuildVectorType()
8063 unsigned VecSize = static_cast<unsigned>(SveVectorSizeInBits.getZExtValue()); in HandleArmSveVectorBitsTypeAttr() local
8066 if (VecSize != S.getLangOpts().VScaleMin * 128) { in HandleArmSveVectorBitsTypeAttr()
8068 << VecSize << S.getLangOpts().VScaleMin * 128; in HandleArmSveVectorBitsTypeAttr()
8088 VecSize /= S.Context.getCharWidth() * S.Context.getCharWidth(); in HandleArmSveVectorBitsTypeAttr()
8091 VecSize /= TypeSize; in HandleArmSveVectorBitsTypeAttr()
8092 CurType = S.Context.getVectorType(EltType, VecSize, VecKind); in HandleArmSveVectorBitsTypeAttr()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DTargetInfo.cpp1102 unsigned VecSize = Context.getTypeSize(VT); in isX86VectorTypeForVectorCall() local
1103 if (VecSize == 128 || VecSize == 256 || VecSize == 512) in isX86VectorTypeForVectorCall()
5970 unsigned VecSize = getContext().getTypeSize(VT); in isHomogeneousAggregateBaseType() local
5971 if (VecSize == 64 || VecSize == 128) in isHomogeneousAggregateBaseType()
7013 unsigned VecSize = getContext().getTypeSize(VT); in isHomogeneousAggregateBaseType() local
7014 if (VecSize == 64 || VecSize == 128) in isHomogeneousAggregateBaseType()
8650 uint64_t VecSize = T.hasFeature("hvx-length64b") ? 64*8 : 128*8; in classifyReturnType() local
8651 if (Size == VecSize || Size == 2*VecSize) in classifyReturnType()
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp1150 int VecSize = in isShuffleEquivalentToSelect() local
1154 if (MaskSize != VecSize) in isShuffleEquivalentToSelect()
1161 if (Elt != -1 && Elt != i && Elt != i + VecSize) in isShuffleEquivalentToSelect()
/llvm-project-15.0.7/llvm/lib/IR/
H A DConstants.cpp1283 unsigned VecSize = V.size(); in getTypeForElements() local
1284 SmallVector<Type*, 16> EltTypes(VecSize); in getTypeForElements()
1285 for (unsigned i = 0; i != VecSize; ++i) in getTypeForElements()
/llvm-project-15.0.7/llvm/unittests/Target/ARM/
H A DMachineInstrTest.cpp2097 int Size = (Flags & ARMII::VecSize) >> ARMII::VecSizeShift; in TEST()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp5309 unsigned VecSize = DstTy.getSizeInBits(); in selectInsertElt() local
5330 if (VecSize < 128) { in selectInsertElt()
5334 emitScalarToVector(VecSize, &AArch64::FPR128RegClass, SrcReg, MIB); in selectInsertElt()
5346 if (VecSize < 128) { in selectInsertElt()
5360 LLVM_DEBUG(dbgs() << "Unsupported destination size! (" << VecSize in selectInsertElt()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMLowOverheadLoops.cpp105 return (Flags & ARMII::VecSize) >> ARMII::VecSizeShift; in getVecSize()
H A DARMInstrFormats.td413 bits<2> VecSize = 0;
434 let TSFlags{25-24} = VecSize;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6712 const unsigned VecSize = 16; in CC_AIX() local
6713 const Align VecAlign(VecSize); in CC_AIX()
6725 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX()
6754 for (unsigned I = 0; I != VecSize; I += PtrSize) in CC_AIX()
6756 State.AllocateStack(VecSize, VecAlign); in CC_AIX()
6760 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX()
6767 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX()
6776 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX()
6794 const unsigned Offset = State.AllocateStack(VecSize, VecAlign); in CC_AIX()
6797 for (unsigned I = 0; I != VecSize; I += PtrSize) { in CC_AIX()

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