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Searched refs:VTList (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h996 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
1002 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
1025 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList);
1026 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N);
1163 SDVTList VTList, ArrayRef<SDValue> Ops,
1171 unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
1178 unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
1184 return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo,
1647 SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList,
1649 SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList,
[all …]
H A DTargetRegisterInfo.h240 vt_iterator VTList; member
317 return getRegClassInfo(RC).VTList; in legalclasstypes_begin()
H A DSelectionDAGISel.h332 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp600 ID.AddPointer(VTList.VTs); in AddNodeIDValueTypes()
624 AddNodeIDValueTypes(ID, VTList); in AddNodeIDNode()
7628 if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) { in getMemIntrinsicNode()
9059 if (VTList.NumVTs == 1) in getNode()
9075 assert(VTList.VTs[0].isInteger() && VTList.VTs[1].isInteger() && in getNode()
9094 assert(VTList.VTs[0].isInteger() && VTList.VTs[0] == VTList.VTs[1] && in getNode()
9108 assert((!VTList.VTs[0].isVector() || in getNode()
9120 assert((!VTList.VTs[0].isVector() || in getNode()
9156 if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) { in getNode()
9801 if (VTList.VTs[VTList.NumVTs - 1] != MVT::Glue) { in getNodeIfExists()
[all …]
H A DLegalizeIntegerTypes.cpp2939 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); in ExpandIntRes_ADDSUB() local
2941 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
2943 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
2945 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
2947 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
2960 SDVTList VTList = DAG.getVTList(NVT, OvfVT); in ExpandIntRes_ADDSUB() local
3038 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
3040 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
3042 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
3044 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
[all …]
H A DSelectionDAGISel.cpp2434 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, in MorphNode() argument
2455 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops); in MorphNode()
3465 SDVTList VTList; in SelectCodeCommon() local
3467 VTList = CurDAG->getVTList(VTs[0]); in SelectCodeCommon()
3469 VTList = CurDAG->getVTList(VTs[0], VTs[1]); in SelectCodeCommon()
3471 VTList = CurDAG->getVTList(VTs); in SelectCodeCommon()
3525 VTList, Ops); in SelectCodeCommon()
3544 Res = cast<MachineSDNode>(MorphNode(NodeToMatch, TargetOpc, VTList, in SelectCodeCommon()
H A DScheduleDAGSDNodes.cpp145 SDVTList VTList = DAG->getVTList(VTs); in CloneNodeWithValues() local
153 DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops); in CloneNodeWithValues()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp229 SDVTList VTList = CurDAG->getVTList(VT, MVT::Other); in matchLoadD16FromBuildVector() local
245 CurDAG->getMemIntrinsicNode(LoadOp, SDLoc(LdHi), VTList, in matchLoadD16FromBuildVector()
263 SDVTList VTList = CurDAG->getVTList(VT, MVT::Other); in matchLoadD16FromBuildVector() local
279 CurDAG->getMemIntrinsicNode(LoadOp, SDLoc(LdLo), VTList, in matchLoadD16FromBuildVector()
853 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue); in SelectADD_SUB_I64() local
867 AddLo = CurDAG->getMachineNode(Opc, DL, VTList, Args); in SelectADD_SUB_I64()
870 AddLo = CurDAG->getMachineNode(CarryOpc, DL, VTList, Args); in SelectADD_SUB_I64()
877 SDNode *AddHi = CurDAG->getMachineNode(CarryOpc, DL, VTList, AddHiArgs); in SelectADD_SUB_I64()
H A DSIISelLowering.h123 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
H A DSIISelLowering.cpp4826 VTList, Ops, M->getMemoryVT(), in adjustLoadValueType()
4861 SDVTList VTList = DAG.getVTList(CastVT, MVT::Other); in lowerIntrinsicLoad() local
6721 SDVTList VTList = DAG.getVTList({LoadVT, MVT::Glue}); in lowerSBuffer() local
7868 EVT VT = VTList.VTs[0]; in getMemIntrinsicNode()
7880 assert(VTList.NumVTs == 2); in getMemIntrinsicNode()
8892 return DAG.getNode(Opcode, SL, VTList, in getFPBinOp()
8914 return DAG.getNode(Opcode, SL, VTList, in getFPTernOp()
11018 SDVTList VTList = DAG.getVTList(MVT::i32, MVT::i1); in performAddCombine() local
11021 return DAG.getNode(Opc, SL, VTList, Args); in performAddCombine()
11059 SDVTList VTList = DAG.getVTList(MVT::i32, MVT::i1); in performSubCombine() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2645 SDVTList VTList = DAG.getVTList(VT, VT); in lowerShiftRightParts() local
2648 DL, VTList, Cond, ShiftRightHi, in lowerShiftRightParts()
2667 SDVTList VTList = DAG.getVTList(VT, MVT::Other); in createLoadLR() local
2674 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, in createLoadLR()
2748 SDVTList VTList = DAG.getVTList(MVT::Other); in createStoreLR() local
2755 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, in createStoreLR()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.h203 TypeSetByHwMode(ArrayRef<ValueTypeByHwMode> VTList);
H A DCodeGenDAGPatterns.cpp84 TypeSetByHwMode::TypeSetByHwMode(ArrayRef<ValueTypeByHwMode> VTList) { in TypeSetByHwMode() argument
85 for (const ValueTypeByHwMode &VVT : VTList) { in TypeSetByHwMode()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4235 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other); in lowerATOMIC_LOAD_OP() local
4238 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops, in lowerATOMIC_LOAD_OP()
4338 SDVTList VTList = DAG.getVTList(WideVT, MVT::i32, MVT::Other); in lowerATOMIC_CMP_SWAP() local
4342 VTList, Ops, NarrowVT, MMO); in lowerATOMIC_CMP_SWAP()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp5646 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); in OptimizeVFPBrcond() local
5648 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops); in OptimizeVFPBrcond()
5763 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); in LowerBR_CC() local
5765 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); in LowerBR_CC()
5769 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); in LowerBR_CC()