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Searched refs:VECTOR_SHUFFLE (Results 1 – 25 of 30) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1213 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
1214 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
1215 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, in getShuffleCost()
1216 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, in getShuffleCost()
1217 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1}, in getShuffleCost()
1218 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, in getShuffleCost()
1220 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, in getShuffleCost()
1221 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, in getShuffleCost()
1222 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, in getShuffleCost()
1234 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
[all …]
H A DARMISelLowering.cpp184 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForNEON()
251 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
330 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
399 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
441 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
1013 {ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, ISD::INSERT_SUBVECTOR, in ARMTargetLowering()
10387 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG, Subtarget); in LowerOperation()
18329 N->getOperand(0).getOpcode() == ISD::VECTOR_SHUFFLE && in PerformMVETruncCombine()
18330 N->getOperand(1).getOpcode() == ISD::VECTOR_SHUFFLE) { in PerformMVETruncCombine()
18359 Op.getOpcode() == ISD::VECTOR_SHUFFLE || in PerformMVETruncCombine()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h586 VECTOR_SHUFFLE, enumerator
H A DSelectionDAGNodes.h1520 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1565 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp87 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); in initializeHVXLowering()
88 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); in initializeHVXLowering()
127 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v128f16, ByteW); in initializeHVXLowering()
128 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f16, ByteV); in initializeHVXLowering()
129 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f32, ByteW); in initializeHVXLowering()
130 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v32f32, ByteV); in initializeHVXLowering()
213 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV); in initializeHVXLowering()
280 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW); in initializeHVXLowering()
H A DHexagonISelLowering.cpp1646 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE, in HexagonTargetLowering()
1748 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in HexagonTargetLowering()
1749 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in HexagonTargetLowering()
1750 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in HexagonTargetLowering()
3205 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAG.cpp910 case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N); in Select()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVECustomDAG.cpp255 case ISD::VECTOR_SHUFFLE: in getIdiomaticVectorType()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp161 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in WebAssemblyTargetLowering()
195 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); in WebAssemblyTargetLowering()
1423 case ISD::VECTOR_SHUFFLE: in LowerOperation()
2739 case ISD::VECTOR_SHUFFLE: in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp296 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; in getOperationName()
H A DDAGCombiner.cpp1787 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); in visit()
19878 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
19912 TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) { in visitEXTRACT_VECTOR_ELT()
22952 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
22953 N0.getOpcode() != ISD::VECTOR_SHUFFLE) { in visitVECTOR_SHUFFLE()
22970 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
22971 N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
23026 (Op00.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
23027 Op10.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
23028 Op01.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
[all …]
H A DSelectionDAG.cpp832 case ISD::VECTOR_SHUFFLE: { in AddNodeIDCustom()
2026 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops); in getVectorShuffle()
2618 case ISD::VECTOR_SHUFFLE: { in isSplatValue()
2775 case ISD::VECTOR_SHUFFLE: { in getSplatSourceVector()
2971 case ISD::VECTOR_SHUFFLE: { in computeKnownBits()
3979 case ISD::VECTOR_SHUFFLE: { in ComputeNumSignBits()
6451 case ISD::VECTOR_SHUFFLE: in getNode()
H A DLegalizeVectorTypes.cpp68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; in ScalarizeVectorResult()
992 case ISD::VECTOR_SHUFFLE: in SplitVectorResult()
3680 case ISD::VECTOR_SHUFFLE: in WidenVectorResult()
H A DLegalizeDAG.cpp3035 case ISD::VECTOR_SHUFFLE: { in ExpandNode()
4646 case ISD::VECTOR_SHUFFLE: { in PromoteNode()
H A DTargetLowering.cpp868 case ISD::VECTOR_SHUFFLE: { in SimplifyMultipleUseDemandedBits()
1288 case ISD::VECTOR_SHUFFLE: { in SimplifyDemandedBits()
3178 case ISD::VECTOR_SHUFFLE: { in SimplifyDemandedVectorElts()
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvext.ll252 ; this rather than blindly emitting a VECTOR_SHUFFLE (infinite
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp355 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in SystemZTargetLowering()
651 ISD::VECTOR_SHUFFLE, in SystemZTargetLowering()
4938 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) { in add()
5791 case ISD::VECTOR_SHUFFLE: in LowerOperation()
6065 else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) && in combineExtract()
6427 Op1.getOpcode() == ISD::VECTOR_SHUFFLE && in combineSTORE()
7135 case ISD::VECTOR_SHUFFLE: return combineVECTOR_SHUFFLE(N, DCI); in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp804 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); in PPCTargetLowering()
805 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
880 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); in PPCTargetLowering()
1081 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); in PPCTargetLowering()
1373 setTargetDAGCombine({ISD::TRUNCATE, ISD::VECTOR_SHUFFLE}); in PPCTargetLowering()
11194 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
14878 if (Mask[0] >= NumElts && LHS.getOpcode() != ISD::VECTOR_SHUFFLE && in combineVectorShuffle()
14879 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) { in combineVectorShuffle()
15149 case ISD::VECTOR_SHUFFLE: in PerformDAGCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1836 case ShuffleVector: return ISD::VECTOR_SHUFFLE; in InstructionOpcodeToISD()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp344 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); in addMSAIntType()
460 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrFragmentsSIMD.td322 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
H A DX86ISelLowering.cpp1089 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1096 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1532 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1641 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1875 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2325 setTargetDAGCombine({ISD::VECTOR_SHUFFLE, in X86TargetLowering()
8214 case ISD::VECTOR_SHUFFLE: { in getFauxShuffleMask()
11129 isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))) { in LowerBUILD_VECTOR()
40567 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in isAddSubOrSubAdd()
40620 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in combineShuffleToFMAddSub()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp386 ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
402 ISD::VSELECT, ISD::SELECT_CC, ISD::FCOPYSIGN, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td684 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp814 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in RISCVTargetLowering()
885 ISD::VECTOR_SHUFFLE, ISD::INSERT_VECTOR_ELT, in RISCVTargetLowering()
3472 case ISD::VECTOR_SHUFFLE: in LowerOperation()

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