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Searched refs:UseMI (Results 1 – 25 of 76) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp24 MachineInstr *UseMI; member
158 if (TII->isMUBUF(UseMI)) in frameIndexMayFold()
161 if (!TII->isFLATScratch(UseMI)) in frameIndexMayFold()
182 MachineInstr *MI = Fold.UseMI; in updateOperand()
312 if (Candidate.UseMI == MI) in isUseMIInFoldList()
593 MachineInstr *UseMI, in foldOperand() argument
611 if (UseMI->isRegSequence()) { in foldOperand()
724 UseMI->removeOperand(UseMI->getOperandNo(Tmp)); in foldOperand()
1229 for (auto &UseMI : in foldInstOperand() local
1251 foldOperand(OpToFold, UseMI, UseMI->getOperandNo(U), FoldList, in foldInstOperand()
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H A DSIOptimizeVGPRLiveRange.cpp215 if (UseMI.getParent() == MBB && !UseMI.isPHI()) in findNonPHIUsesInBlock()
216 Uses.push_back(&UseMI); in findNonPHIUsesInBlock()
305 auto *UseMI = I->getParent(); in collectCandidateRegisters() local
306 auto *UseMBB = UseMI->getParent(); in collectCandidateRegisters()
308 if (!UseMI->isPHI()) in collectCandidateRegisters()
430 auto *UseMI = I->getParent(); in updateLiveRangeInThenRegion() local
431 if (UseMI->isPHI() && I->readsReg()) { in updateLiveRangeInThenRegion()
521 auto *UseMI = O.getParent(); in optimizeLiveRange() local
522 auto *UseBlock = UseMI->getParent(); in optimizeLiveRange()
556 auto *UseMI = O.getParent(); in optimizeWaterfallLiveRange() local
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H A DSIFixSGPRCopies.cpp194 const auto *UseMI = MO.getParent(); in tryChangeVGPRtoSGPRinCopy() local
195 if (UseMI == &MI) in tryChangeVGPRtoSGPRinCopy()
201 unsigned OpIdx = UseMI->getOperandNo(&MO); in tryChangeVGPRtoSGPRinCopy()
203 !TII->isOperandLegal(*UseMI, OpIdx, &Src)) in tryChangeVGPRtoSGPRinCopy()
803 AllAGPRUses &= (UseMI->isCopy() && in processPHINode()
806 if (UseMI->isCopy() || UseMI->isRegSequence()) { in processPHINode()
807 if (UseMI->isCopy() && in processPHINode()
812 if (Visited.insert(UseMI).second) in processPHINode()
813 worklist.insert(UseMI); in processPHINode()
818 if (UseMI->isPHI()) { in processPHINode()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp193 MI.getParent() != UseMI.getParent()) in canRemoveAddasl()
199 getBaseWithLongOffset(UseMI) < 0) in canRemoveAddasl()
207 for (auto &Mo : UseMI.operands()) in canRemoveAddasl()
475 Changed |= updateAddUses(AddMI, UseMI); in processAddUses()
496 MachineOperand &BaseOp = UseMI->getOperand(getBaseOpPosition(UseMI)); in updateAddUses()
497 MachineOperand &OffsetOp = UseMI->getOperand(getOffsetOpPosition(UseMI)); in updateAddUses()
718 MIB.add(UseMI->getOperand(0)); in changeAddAsl()
731 MIB.add(UseMI->getOperand(2)); in changeAddAsl()
737 MIB.add(UseMI->getOperand(i)); in changeAddAsl()
739 Deleted.insert(UseMI); in changeAddAsl()
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineTraceMetrics.cpp655 if (UseMI.isDebugInstr()) in getDataDeps()
660 E = UseMI.operands_end(); I != E; ++I) { in getDataDeps()
688 assert(UseMI.isPHI() && UseMI.getNumOperands() % 2 && "Bad PHI"); in getPHIDeps()
745 LRU.MI = UseMI; in updatePhysDepsDownwards()
786 if (UseMI.isPHI()) in updateDepth()
787 getPHIDeps(UseMI, Deps, TBI.Pred, MTM.MRI); in updateDepth()
788 else if (getDataDeps(UseMI, Deps, MTM.MRI)) in updateDepth()
808 InstrCycles &MICycles = Cycles[&UseMI]; in updateDepth()
883 for (const auto &UseMI : *MBB) { in computeInstrDepths()
884 updateDepth(TBI, UseMI, RegUnits); in computeInstrDepths()
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H A DLiveRangeEdit.cpp202 MachineInstr *DefMI = nullptr, *UseMI = nullptr; in foldAsLoad() local
214 if (UseMI && UseMI != MI) in foldAsLoad()
219 UseMI = MI; in foldAsLoad()
222 if (!DefMI || !UseMI) in foldAsLoad()
228 LIS.getInstructionIndex(*UseMI))) in foldAsLoad()
238 << " into single use: " << *UseMI); in foldAsLoad()
241 if (UseMI->readsWritesVirtualRegister(LI->reg(), &Ops).second) in foldAsLoad()
248 LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI); in foldAsLoad()
250 if (UseMI->shouldUpdateCallSiteInfo()) in foldAsLoad()
251 UseMI->getMF()->moveCallSiteInfo(UseMI, FoldMI); in foldAsLoad()
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H A DTargetSchedule.cpp185 const MachineInstr *UseMI, unsigned UseOperIdx) const { in computeOperandLatency() argument
192 if (UseMI) { in computeOperandLatency()
194 *UseMI, UseOperIdx); in computeOperandLatency()
224 if (!UseMI) in computeOperandLatency()
228 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI); in computeOperandLatency()
231 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); in computeOperandLatency()
H A DRegisterScavenging.cpp288 MachineBasicBlock::iterator &UseMI) { in findSurvivorReg() argument
345 UseMI = RestorePointMI; in findSurvivorReg()
447 MachineBasicBlock::iterator &UseMI) { in spill() argument
492 if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) { in spill()
509 TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, TRI); in spill()
510 II = std::prev(UseMI); in spill()
558 MachineBasicBlock::iterator UseMI; in scavengeRegister() local
559 Register SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister()
576 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI); in scavengeRegister()
577 Scavenged.Restore = &*std::prev(UseMI); in scavengeRegister()
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H A DMachineLICM.cpp962 if (UseMI.mayStore() && isInvariantStore(UseMI, TRI, MRI)) in isCopyFeedingInvariantStore()
1025 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) { in HasLoopPHIUse()
1027 if (UseMI.isPHI()) { in HasLoopPHIUse()
1030 if (CurLoop->contains(&UseMI)) in HasLoopPHIUse()
1035 if (isExitBlock(UseMI.getParent())) in HasLoopPHIUse()
1040 if (UseMI.isCopy() && CurLoop->contains(&UseMI)) in HasLoopPHIUse()
1041 Work.push_back(&UseMI); in HasLoopPHIUse()
1055 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) { in HasHighOperandLatency()
1056 if (UseMI.isCopyLike()) in HasHighOperandLatency()
1058 if (!CurLoop->contains(UseMI.getParent())) in HasHighOperandLatency()
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H A DDetectDeadLanes.cpp417 const MachineInstr &UseMI = *MO.getParent(); in determineInitialUsedLanes() local
418 if (UseMI.isKill()) in determineInitialUsedLanes()
422 if (lowersToCopies(UseMI)) { in determineInitialUsedLanes()
423 assert(UseMI.getDesc().getNumDefs() == 1); in determineInitialUsedLanes()
424 const MachineOperand &Def = *UseMI.defs().begin(); in determineInitialUsedLanes()
431 if (lowersToCopies(UseMI)) { in determineInitialUsedLanes()
433 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes()
435 LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI); in determineInitialUsedLanes()
H A DOptimizePHIs.cpp156 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) { in IsDeadPHICycle()
157 if (!UseMI.isPHI() || !IsDeadPHICycle(&UseMI, PHIsInCycle)) in IsDeadPHICycle()
H A DMachineSSAUpdater.cpp235 MachineInstr *UseMI = U.getParent(); in RewriteUse() local
237 if (UseMI->isPHI()) { in RewriteUse()
238 MachineBasicBlock *SourceBB = findCorrespondingPred(UseMI, &U); in RewriteUse()
241 NewVR = GetValueInMiddleOfBlock(UseMI->getParent()); in RewriteUse()
H A DTailDuplicator.cpp218 MachineInstr *UseMI = UseMO.getParent(); in tailDuplicateAndUpdate() local
223 if (UseMI->isDebugValue()) { in tailDuplicateAndUpdate()
227 if (UseMI->getParent() == DefBB && !UseMI->isPHI()) in tailDuplicateAndUpdate()
232 MachineInstr *UseMI = UseMO->getParent(); in tailDuplicateAndUpdate() local
234 SSAUpdate.GetValueInMiddleOfBlock(UseMI->getParent(), true)); in tailDuplicateAndUpdate()
299 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) { in isDefLiveOut()
300 if (UseMI.isDebugValue()) in isDefLiveOut()
302 if (UseMI.getParent() != BB) in isDefLiveOut()
H A DPeepholeOptimizer.cpp504 MachineInstr *UseMI = UseMO.getParent(); in INITIALIZE_PASS_DEPENDENCY() local
505 if (UseMI == &MI) in INITIALIZE_PASS_DEPENDENCY()
508 if (UseMI->isPHI()) { in INITIALIZE_PASS_DEPENDENCY()
534 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) in INITIALIZE_PASS_DEPENDENCY()
537 MachineBasicBlock *UseMBB = UseMI->getParent(); in INITIALIZE_PASS_DEPENDENCY()
540 if (!LocalMIs.count(UseMI)) in INITIALIZE_PASS_DEPENDENCY()
577 MachineInstr *UseMI = UseMO->getParent(); in INITIALIZE_PASS_DEPENDENCY() local
578 MachineBasicBlock *UseMBB = UseMI->getParent(); in INITIALIZE_PASS_DEPENDENCY()
603 RC = MRI->getRegClass(UseMI->getOperand(0).getReg()); in INITIALIZE_PASS_DEPENDENCY()
606 BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(), in INITIALIZE_PASS_DEPENDENCY()
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H A DRegisterCoalescer.cpp893 MachineInstr *UseMI = MO.getParent(); in removeCopyByCommutingDef() local
940 if (UseMI->isDebugInstr()) { in removeCopyByCommutingDef()
957 if (UseMI == CopyMI) in removeCopyByCommutingDef()
959 if (!UseMI->isCopy()) in removeCopyByCommutingDef()
962 UseMI->getOperand(0).getSubReg()) in removeCopyByCommutingDef()
983 deleteInstr(UseMI); in removeCopyByCommutingDef()
1575 if (UseMI->isDebugInstr()) { in reMaterializeTrivialDef()
1582 MBB->splice(std::next(NewMI.getIterator()), UseMI->getParent(), UseMI); in reMaterializeTrivialDef()
1767 MachineInstr *UseMI = &*(I++); in updateRegDefsUses() local
1829 if (!UseMI->isDebugInstr()) in updateRegDefsUses()
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H A DTwoAddressInstructionPass.cpp392 MachineInstr &UseMI = *UseOp->getParent(); in findOnlyInterestingUse() local
398 return &UseMI; in findOnlyInterestingUse()
401 if (isTwoAddrUse(UseMI, Reg, DstReg)) { in findOnlyInterestingUse()
403 return &UseMI; in findOnlyInterestingUse()
405 if (UseMI.isCommutable()) { in findOnlyInterestingUse()
407 unsigned Src2 = UseMI.getOperandNo(UseOp); in findOnlyInterestingUse()
408 if (TII->findCommutedOpIndices(UseMI, Src1, Src2)) { in findOnlyInterestingUse()
409 MachineOperand &MO = UseMI.getOperand(Src1); in findOnlyInterestingUse()
411 isTwoAddrUse(UseMI, MO.getReg(), DstReg)) { in findOnlyInterestingUse()
413 return &UseMI; in findOnlyInterestingUse()
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H A DModuloSchedule.cpp85 MachineInstr *UseMI = UseOp.getParent(); in expand() local
86 int UseStage = Schedule.getStage(UseMI); in expand()
1131 MachineInstr *UseMI = UseOp.getParent(); in rewriteScheduledInstr() local
1132 if (UseMI->getParent() != BB) in rewriteScheduledInstr()
1134 if (UseMI->isPHI()) { in rewriteScheduledInstr()
1137 if (getLoopPhiReg(*UseMI, BB) != OldReg) in rewriteScheduledInstr()
1172 BuildMI(*BB, UseMI, UseMI->getDebugLoc(), TII->get(TargetOpcode::COPY), in rewriteScheduledInstr()
1605 assert(UseMI.isPHI()); in filterInstructions()
1608 Subs.emplace_back(&UseMI, Reg); in filterInstructions()
1919 assert(UseMI.isPHI()); in rewriteUsesOf()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp324 for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) { in detectAndFoldOffset() local
325 switch (UseMI.getOpcode()) { in detectAndFoldOffset()
327 LLVM_DEBUG(dbgs() << "Not a load or store instruction: " << UseMI); in detectAndFoldOffset()
346 if (UseMI.getOperand(1).isFI()) in detectAndFoldOffset()
349 if (DestReg == UseMI.getOperand(0).getReg()) in detectAndFoldOffset()
351 assert(DestReg == UseMI.getOperand(1).getReg() && in detectAndFoldOffset()
354 int64_t Offset = UseMI.getOperand(2).getImm(); in detectAndFoldOffset()
369 for (MachineInstr &UseMI : in detectAndFoldOffset()
371 UseMI.removeOperand(2); in detectAndFoldOffset()
372 UseMI.addOperand(ImmOp); in detectAndFoldOffset()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastPreTileConfig.cpp232 if (UseMI->isCopy()) in reload()
233 TileReg = UseMI->getOperand(0).getReg(); in reload()
242 MachineInstr *NewMI = BuildMI(*UseMI->getParent(), UseMI, DebugLoc(), in reload()
246 BuildMI(*UseMI->getParent(), UseMI, DebugLoc(), TII->get(Opc), TileReg) in reload()
256 if (UseMI->isCopy()) { in reload()
257 UseMI->eraseFromParent(); in reload()
260 for (auto &MO : UseMI->operands()) { in reload()
626 if (UseMI.getParent() == &MBB) { in configBasicBlock()
631 reload(UseMI.getIterator(), TileReg, RowMO, ColMO); in configBasicBlock()
635 if (!UseMI.isPHI()) in configBasicBlock()
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H A DX86SpeculativeLoadHardening.cpp1791 for (MachineInstr &UseMI : MRI->use_instructions(DefReg)) { in sinkPostLoadHardenedInst()
1794 if (HardenedInstrs.count(&UseMI)) { in sinkPostLoadHardenedInst()
1795 if (!X86InstrInfo::isDataInvariantLoad(UseMI) || isEFLAGSDefLive(UseMI)) { in sinkPostLoadHardenedInst()
1799 assert(X86InstrInfo::isDataInvariant(UseMI) && in sinkPostLoadHardenedInst()
1806 const MCInstrDesc &Desc = UseMI.getDesc(); in sinkPostLoadHardenedInst()
1813 UseMI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in sinkPostLoadHardenedInst()
1831 if (!X86InstrInfo::isDataInvariant(UseMI) || UseMI.getParent() != MI.getParent() || in sinkPostLoadHardenedInst()
1832 isEFLAGSDefLive(UseMI)) in sinkPostLoadHardenedInst()
1837 if (UseMI.getDesc().getNumDefs() > 1) in sinkPostLoadHardenedInst()
1843 Register UseDefReg = UseMI.getOperand(0).getReg(); in sinkPostLoadHardenedInst()
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/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLocalizer.cpp126 MachineInstr &UseMI = *MOUse.getParent(); in localizeInterBlock() local
127 if (MRI->hasOneUse(Reg) && !UseMI.isPHI()) in localizeInterBlock()
128 InsertMBB->insert(UseMI, LocalizedMI); in localizeInterBlock()
163 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) { in localizeIntraBlock()
164 if (!UseMI.isPHI()) in localizeIntraBlock()
165 Users.insert(&UseMI); in localizeIntraBlock()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp122 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg() local
123 if (UseMI->getParent() != MBB) in getDefReg()
126 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()
127 Reg = UseMI->getOperand(0).getReg(); in getDefReg()
130 UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg()
131 if (UseMI->getParent() != MBB) in getDefReg()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp679 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
680 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs()
692 LLVM_DEBUG(UseMI.dump()); in recordUnoptimizableWebs()
701 Register SwapDefReg = UseMI.getOperand(0).getReg(); in recordUnoptimizableWebs()
713 LLVM_DEBUG(UseMI.dump()); in recordUnoptimizableWebs()
745 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
746 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs()
787 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
788 int UseIdx = SwapMap[&UseMI]; in markSwapsForRemoval()
792 LLVM_DEBUG(UseMI.dump()); in markSwapsForRemoval()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips16RegisterInfo.cpp58 MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, in saveScavengerRegister() argument
63 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true); in saveScavengerRegister()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp576 bool VEInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, in FoldImmediate() argument
637 LLVM_DEBUG(UseMI.dump()); in FoldImmediate()
659 switch (UseMI.getOpcode()) { in FoldImmediate()
706 if (UseMI.getOperand(1).getReg() == Reg) { in FoldImmediate()
709 assert(UseMI.getOperand(2).getReg() == Reg); in FoldImmediate()
723 if (UseMI.getOperand(1).getReg() == Reg) { in FoldImmediate()
730 assert(UseMI.getOperand(2).getReg() == Reg); in FoldImmediate()
743 UseMI.setDesc(get(NewUseOpc)); in FoldImmediate()
745 UseMI.getOperand(1).setReg(UseMI.getOperand(UseIdx).getReg()); in FoldImmediate()
747 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal); in FoldImmediate()

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