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Searched refs:UADDSAT (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-uaddsat.mir38 ; GFX8-NEXT: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]]
39 ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16)
52 ; GFX9-NEXT: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]]
53 ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16)
258 ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDSAT]](s16)
331 ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT]](s16)
343 ; GFX9-NEXT: $vgpr0 = COPY [[UADDSAT]](<2 x s16>)
436 ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT]](s16)
582 ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT]](s16)
633 ; GFX8-NEXT: $vgpr0 = COPY [[UADDSAT]](s32)
[all …]
H A Dirtranslator-sat.ll13 ; CHECK-NEXT: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC1]]
14 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDSAT]](s16)
29 ; CHECK-NEXT: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[COPY]], [[COPY1]]
30 ; CHECK-NEXT: $vgpr0 = COPY [[UADDSAT]](s32)
48 ; CHECK-NEXT: [[UADDSAT:%[0-9]+]]:_(s64) = G_UADDSAT [[MV]], [[MV1]]
49 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](s64)
69 ; CHECK-NEXT: [[UADDSAT:%[0-9]+]]:_(<2 x s32>) = G_UADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
70 …; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](<2 x …
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h341 UADDSAT, enumerator
H A DTargetLowering.h2624 case ISD::UADDSAT: in isCommutativeBinOp()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2926 { ISD::UADDSAT, MVT::v32i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2927 { ISD::UADDSAT, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2989 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd in getTypeBasedIntrinsicInstrCost()
2990 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq in getTypeBasedIntrinsicInstrCost()
2997 { ISD::UADDSAT, MVT::v32i16, 2 }, in getTypeBasedIntrinsicInstrCost()
2998 { ISD::UADDSAT, MVT::v64i8, 2 }, in getTypeBasedIntrinsicInstrCost()
3074 { ISD::UADDSAT, MVT::v16i16, 1 }, in getTypeBasedIntrinsicInstrCost()
3075 { ISD::UADDSAT, MVT::v32i8, 1 }, in getTypeBasedIntrinsicInstrCost()
3237 { ISD::UADDSAT, MVT::v8i16, 1 }, in getTypeBasedIntrinsicInstrCost()
3238 { ISD::UADDSAT, MVT::v16i8, 1 }, in getTypeBasedIntrinsicInstrCost()
[all …]
H A DX86ISelLowering.cpp1057 setOperationAction(ISD::UADDSAT, MVT::v16i8, Legal); in X86TargetLowering()
1061 setOperationAction(ISD::UADDSAT, MVT::v8i16, Legal); in X86TargetLowering()
1253 setOperationAction(ISD::UADDSAT, MVT::v4i32, Custom); in X86TargetLowering()
1295 setOperationAction(ISD::UADDSAT, MVT::v2i64, Custom); in X86TargetLowering()
1472 setOperationAction(ISD::UADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom); in X86TargetLowering()
1476 setOperationAction(ISD::UADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
1480 setOperationAction(ISD::UADDSAT, MVT::v8i32, Custom); in X86TargetLowering()
1482 setOperationAction(ISD::UADDSAT, MVT::v4i64, Custom); in X86TargetLowering()
1827 setOperationAction(ISD::UADDSAT, VT, HasBWI ? Legal : Custom); in X86TargetLowering()
32338 case ISD::UADDSAT: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp405 case ISD::UADDSAT: in LegalizeOp()
843 case ISD::UADDSAT: in Expand()
H A DSelectionDAGDumper.cpp322 case ISD::UADDSAT: return "uaddsat"; in getOperationName()
H A DLegalizeIntegerTypes.cpp194 case ISD::UADDSAT: in PromoteIntegerResult()
869 } else if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) { in PromoteIntRes_ADDSUBSHLSAT()
879 if (Opcode == ISD::UADDSAT) { in PromoteIntRes_ADDSUBSHLSAT()
2521 case ISD::UADDSAT: in ExpandIntegerResult()
H A DLegalizeVectorTypes.cpp133 case ISD::UADDSAT: in ScalarizeVectorResult()
1091 case ISD::UADDSAT: in SplitVectorResult()
3715 case ISD::UADDSAT: in WidenVectorResult()
H A DSelectionDAG.cpp5450 case ISD::UADDSAT: return C1.uadd_sat(C2); in FoldValue()
5984 case ISD::UADDSAT: in getNode()
5991 if (Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT) in getNode()
6347 case ISD::UADDSAT: in getNode()
H A DLegalizeDAG.cpp1140 case ISD::UADDSAT: in LegalizeOp()
3416 case ISD::UADDSAT: in ExpandNode()
H A DTargetLowering.cpp8878 if (Opcode == ISD::UADDSAT && isOperationLegal(ISD::UMIN, VT)) { in expandAddSubSat()
8889 case ISD::UADDSAT: in expandAddSubSat()
8916 if (Opcode == ISD::UADDSAT) { in expandAddSubSat()
H A DDAGCombiner.cpp1678 case ISD::UADDSAT: return visitADDSAT(N); in visit()
2738 if (Opcode == ISD::UADDSAT) in visitADDSAT()
10939 if (hasOperation(ISD::UADDSAT, VT)) { in visitVSELECT()
10966 return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS); in visitVSELECT()
10980 return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS); in visitVSELECT()
H A DSelectionDAGBuilder.cpp6530 setValue(&I, DAG.getNode(ISD::UADDSAT, sdl, Op1.getValueType(), Op1, Op2)); in visitIntrinsicCall()
7204 ISD::UADDSAT, sdl, VecTy, VectorIndex, VectorStep); in visitIntrinsicCall()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp802 ISD::SADDSAT, ISD::UADDSAT, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp212 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in addTypeForNEON()
271 setOperationAction(ISD::UADDSAT, VT, Legal); in addMVEVectorTypes()
1133 setOperationAction(ISD::UADDSAT, MVT::i8, Custom); in ARMTargetLowering()
1135 setOperationAction(ISD::UADDSAT, MVT::i16, Custom); in ARMTargetLowering()
5036 case ISD::UADDSAT: in LowerADDSUBSAT()
5052 case ISD::UADDSAT: in LowerADDSUBSAT()
7756 case ISD::UADDSAT: in IsQRMVEInstruction()
10416 case ISD::UADDSAT: in LowerOperation()
10520 case ISD::UADDSAT: in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp209 setOperationAction({ISD::UADDO, ISD::USUBO, ISD::UADDSAT, ISD::USUBSAT}, in RISCVTargetLowering()
577 {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, VT, Legal); in RISCVTargetLowering()
837 {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, VT, in RISCVTargetLowering()
3550 case ISD::UADDSAT: in LowerOperation()
7063 case ISD::UADDSAT: in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp429 setOperationAction({ISD::UADDSAT, ISD::USUBSAT}, MVT::i32, Legal); in SITargetLowering()
457 ISD::UMAX, ISD::UADDSAT, ISD::USUBSAT}, in SITargetLowering()
636 ISD::UADDSAT, ISD::USUBSAT, ISD::SADDSAT, ISD::SSUBSAT}, in SITargetLowering()
655 ISD::UADDSAT, ISD::SADDSAT, ISD::USUBSAT, in SITargetLowering()
4737 case ISD::UADDSAT: in LowerOperation()
H A DAMDGPUISelLowering.cpp2274 unsigned AddOpc = ZeroUndef ? ISD::ADD : ISD::UADDSAT; in LowerCTLZ_CTTZ()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp179 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT}) in WebAssemblyTargetLowering()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td423 def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1039 setOperationAction(ISD::UADDSAT, VT, Legal); in AArch64TargetLowering()
1196 setOperationAction(ISD::UADDSAT, VT, Legal); in AArch64TargetLowering()
16641 return convertMergedOpToPredOp(N, ISD::UADDSAT, DAG, true); in performIntrinsicCombine()
16651 return DAG.getNode(ISD::UADDSAT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp757 setOperationAction(ISD::UADDSAT, VT, Legal); in PPCTargetLowering()