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Searched refs:TrueReg (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp647 Register TrueReg = in simplifyCode() local
649 if (!Register::isVirtualRegister(TrueReg)) in simplifyCode()
651 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
711 Register TrueReg = in simplifyCode() local
713 if (!Register::isVirtualRegister(TrueReg)) in simplifyCode()
715 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
H A DPPCInstrInfo.cpp1639 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1640 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
3137 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
3144 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3146 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3148 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
3160 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
3296 Register TrueReg = TRI->lookThruCopyLike(Reg, MRI); in getForwardingDefMI() local
3297 if (Register::isVirtualRegister(TrueReg)) { in getForwardingDefMI()
3298 DefMI = MRI->getVRegDef(TrueReg); in getForwardingDefMI()
[all …]
H A DPPCInstrInfo.h527 ArrayRef<MachineOperand> Cond, Register TrueReg,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp787 auto TrueReg = MIB.getReg(2); in selectSelect() local
789 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) && in selectSelect()
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
794 .addUse(TrueReg) in selectSelect()
H A DARMBaseInstrInfo.cpp2365 MachineOperand TrueReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
2368 const TargetRegisterClass *TrueClass = MRI.getRegClass(TrueReg.getReg()); in optimizeSelect()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp918 Register TrueReg = getRegForValue(Select->getTrueValue()); in selectSelect() local
919 if (TrueReg == 0) in selectSelect()
927 std::swap(TrueReg, FalseReg); in selectSelect()
965 .addReg(TrueReg) in selectSelect()
H A DWebAssemblyISelLowering.cpp473 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
479 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
513 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute); in LowerFPToInt()
517 .addReg(TrueReg) in LowerFPToInt()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp539 Register DstReg, Register TrueReg, in canInsertSelect() argument
552 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
575 Register TrueReg, in insertSelect() argument
595 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
597 TrueReg = TReg; in insertSelect()
609 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
H A DSystemZInstrInfo.h244 ArrayRef<MachineOperand> Cond, Register TrueReg,
H A DSystemZISelLowering.cpp7562 Register TrueReg = MI->getOperand(1).getReg(); in createPHIsForSelects() local
7569 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
7571 if (RegRewriteTable.find(TrueReg) != RegRewriteTable.end()) in createPHIsForSelects()
7572 TrueReg = RegRewriteTable[TrueReg].first; in createPHIsForSelects()
7579 .addReg(TrueReg).addMBB(TrueMBB) in createPHIsForSelects()
7583 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h310 Register TrueReg, Register FalseReg, int &CondCycles,
316 Register TrueReg, Register FalseReg) const override;
321 Register TrueReg, Register FalseReg) const;
H A DSIInstrInfo.cpp1144 .addReg(TrueReg) in insertVectorSelect()
1159 .addReg(TrueReg) in insertVectorSelect()
1173 .addReg(TrueReg) in insertVectorSelect()
1187 .addReg(TrueReg) in insertVectorSelect()
1199 .addReg(TrueReg) in insertVectorSelect()
1219 .addReg(TrueReg) in insertVectorSelect()
1237 .addReg(TrueReg) in insertVectorSelect()
2771 std::swap(TrueReg, FalseReg); in insertSelect()
2782 .addReg(TrueReg) in insertSelect()
2788 .addReg(TrueReg); in insertSelect()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h889 Register TrueReg, Register FalseReg, in canInsertSelect() argument
913 Register TrueReg, Register FalseReg) const { in insertSelect() argument
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h232 ArrayRef<MachineOperand> Cond, Register TrueReg,
H A DAArch64InstrInfo.cpp603 Register DstReg, Register TrueReg, in canInsertSelect() argument
610 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
630 if (canFoldIntoCSel(MRI, TrueReg)) in canInsertSelect()
654 Register TrueReg, Register FalseReg) const { in insertSelect() argument
757 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg); in insertSelect()
762 TrueReg = FalseReg; in insertSelect()
776 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
781 .addReg(TrueReg) in insertSelect()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrInfo.h361 ArrayRef<MachineOperand> Cond, Register TrueReg,
H A DX86InstrInfo.cpp3339 Register DstReg, Register TrueReg, in canInsertSelect() argument
3354 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
3377 ArrayRef<MachineOperand> Cond, Register TrueReg, in insertSelect() argument
3387 .addReg(TrueReg) in insertSelect()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp5578 Register TrueReg = Sel.getTrueReg(); in matchSelectToLogical() local
5581 auto *TrueDef = getDefIgnoringCopies(TrueReg, MRI); in matchSelectToLogical()
5585 const LLT OpTy = MRI.getType(TrueReg); in matchSelectToLogical()
5594 if (Cond == TrueReg || (MaybeCstTrue && MaybeCstTrue->isOne())) { in matchSelectToLogical()
5606 MIB.buildAnd(DstReg, Cond, TrueReg); in matchSelectToLogical()
5614 MIB.buildOr(DstReg, MIB.buildNot(OpTy, Cond), TrueReg); in matchSelectToLogical()