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Searched refs:TargetFrameIndex (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/
H A Dlanai_isel.ll.expected8 ; CHECK-NEXT: t5: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.0)> TargetFrameIndex:i32<-2>…
9 ; CHECK-NEXT: t7: i32 = ADD_I_LO TargetFrameIndex:i32<0>, TargetConstant:i32<0>
13 … t3: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.1, align 8)> TargetFrameIndex:i32<-1>, Targ…
14 …ch = LDW_RI<Mem:(dereferenceable load (s32) from %ir.loc, align 8)> TargetFrameIndex:i32<0>, Targe…
35 … t3: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.0, align 8)> TargetFrameIndex:i32<-1>, Targ…
36 … t6: i32,ch = LDW_RI<Mem:(dereferenceable load (s32) from %ir.loc)> TargetFrameIndex:i32<0>, Targe…
54 ; CHECK-NEXT: t1: i32 = ADD_I_LO TargetFrameIndex:i32<-1>, TargetConstant:i32<0>
57 …22: i32,ch = LDHz_RI<Mem:(dereferenceable load (s16) from %ir.loc)> TargetFrameIndex:i32<0>, Targe…
77 ; CHECK-NEXT: t1: i32 = ADD_I_LO TargetFrameIndex:i32<-1>, TargetConstant:i32<0>
80 …t22: i32,ch = LDBz_RI<Mem:(dereferenceable load (s8) from %ir.loc)> TargetFrameIndex:i32<0>, Targe…
H A Dx86_isel.ll.expected10 …i32,ch = ADD64rm<Mem:(dereferenceable load (s64) from %ir.loc)> t2, TargetFrameIndex:i64<0>, Targe…
19 …i32,ch = ADD64rm<Mem:(dereferenceable load (s64) from %ir.loc)> t2, TargetFrameIndex:i64<0>, Targe…
34 …i32,ch = ADD32rm<Mem:(dereferenceable load (s32) from %ir.loc)> t2, TargetFrameIndex:i64<0>, Targe…
44 …i32,ch = ADD32rm<Mem:(dereferenceable load (s32) from %ir.loc)> t2, TargetFrameIndex:i64<0>, Targe…
62 …i32,ch = ADD16rm<Mem:(dereferenceable load (s16) from %ir.loc)> t3, TargetFrameIndex:i64<0>, Targe…
73 …i32,ch = ADD16rm<Mem:(dereferenceable load (s16) from %ir.loc)> t2, TargetFrameIndex:i64<0>, Targe…
92 …8,i32,ch = ADD8rm<Mem:(dereferenceable load (s8) from %ir.loc)> t3, TargetFrameIndex:i64<0>, Targe…
103 …8,i32,ch = ADD8rm<Mem:(dereferenceable load (s8) from %ir.loc)> t2, TargetFrameIndex:i64<0>, Targe…
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dframeindex.ll9 ; MIPS32: t{{[0-9]+}}: i{{[0-9]+}} = LEA_ADDiu TargetFrameIndex:i32<0>, TargetConstant:i32<0>
10 ; MM: t{{[0-9]+}}: i{{[0-9]+}} = LEA_ADDiu_MM TargetFrameIndex:i32<0>, TargetConstant:i32<0>
11 ; MIPS64: t{{[0-9]+}}: i{{[0-9]+}} = LEA_ADDiu64 TargetFrameIndex:i64<0>, TargetConstant:i64<0>
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fixed-length-frame-offests.ll17 ; CHECK-NEXT: t8: i64 = ADDXri TargetFrameIndex:i64<1>, TargetConstant:i32<0>, TargetConstant:i3…
18 …7: ch = ST1D_IMM<Mem:(volatile store (s512) into %ir.r0)> t18, t12, TargetFrameIndex:i64<0>, Targe…
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h166 TargetFrameIndex, enumerator
H A DSelectionDAGNodes.h1771 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
1780 N->getOpcode() == ISD::TargetFrameIndex;
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp163 case ISD::TargetFrameIndex: return "TargetFrameIndex"; in getOperationName()
H A DSelectionDAGISel.cpp2808 case ISD::TargetFrameIndex: in SelectCodeCommon()
H A DSelectionDAG.cpp670 case ISD::TargetFrameIndex: in AddNodeIDCustom()
1680 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; in getFrameIndex()
3809 case ISD::TargetFrameIndex: in computeKnownBits()
H A DDAGCombiner.cpp23770 LLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || in SimplifySelectOps()
23771 RLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || in SimplifySelectOps()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1725 if (Base.getOpcode() != ISD::TargetFrameIndex && in SelectInlineAsmMemoryOperand()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp1797 SAddr.getOpcode() == ISD::TargetFrameIndex in SelectScratchSAddr()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td359 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],