| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | RegisterBank.cpp | 46 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() local
48 if (!RC.hasSubClassEq(&SubRC)) in verify()
53 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify()
55 assert(covers(SubRC) && "Not all subclasses are covered"); in verify()
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| H A D | TargetRegisterInfo.cpp | 201 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass() local
202 if (SubRC->isAllocatable()) in getAllocatableClass()
203 return SubRC; in getAllocatableClass()
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 986 CodeGenRegisterClass &SubRC = *I2; in computeSubClasses() local
987 if (RC.SubClasses.test(SubRC.EnumValue)) in computeSubClasses()
989 if (!testSubClass(&RC, &SubRC)) in computeSubClasses()
993 RC.SubClasses |= SubRC.SubClasses; in computeSubClasses()
2268 CodeGenRegisterClass *SubRC = in inferSubClassWithSubReg() local
2271 RC->setSubClassWithSubReg(&SubIdx, SubRC); in inferSubClassWithSubReg()
2313 CodeGenRegisterClass &SubRC = *I; in inferMatchingSuperRegClass() local
2314 if (SubRC.Artificial) in inferMatchingSuperRegClass()
2317 if (!TopoSigs.anyCommon(SubRC.getTopoSigs())) in inferMatchingSuperRegClass()
2322 if (SubRC.contains(SSPairs[i].second)) in inferMatchingSuperRegClass()
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| H A D | CodeGenRegisters.h | 398 CodeGenRegisterClass *SubRC) { in setSubClassWithSubReg() argument
399 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
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| H A D | CompressInstEmitter.cpp | 176 const CodeGenRegisterClass &SubRC = Target.getRegisterClass(DagOpType); in validateTypes() local
177 return RC.hasSubClass(&SubRC); in validateTypes()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 262 const TargetRegisterClass *SubRC,
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| H A D | AMDGPUInstructionSelector.h | 84 const TargetRegisterClass &SubRC,
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| H A D | SIFoldOperands.cpp | 897 const TargetRegisterClass *SubRC = TRI->getSubRegClass(RC, SubReg); in foldOperand() local
898 RC = TRI->getCompatibleSubRegClass(RC, SubRC, SubReg); in foldOperand()
900 RC = SubRC; in foldOperand()
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| H A D | SIInstrInfo.h | 73 const TargetRegisterClass *SubRC) const;
79 const TargetRegisterClass *SubRC) const;
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| H A D | SIInstrInfo.cpp | 4106 const TargetRegisterClass *SubRC = in verifyInstruction() local
4108 RC = RI.getCompatibleSubRegClass(RC, SubRC, MO.getSubReg()); in verifyInstruction()
4110 RC = SubRC; in verifyInstruction()
4882 const TargetRegisterClass *SubRC) in buildExtractSubReg()
4886 Register SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg()
4915 const TargetRegisterClass *SubRC) const { in buildExtractSubRegOrImm()
4926 SubIdx, SubRC); in buildExtractSubRegOrImm()
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| H A D | SIRegisterInfo.cpp | 2729 const TargetRegisterClass *SubRC, in getCompatibleSubRegClass() argument
2733 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx); in getCompatibleSubRegClass()
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| H A D | AMDGPUInstructionSelector.cpp | 237 const TargetRegisterClass &SubRC, in getSubOperand64() argument
242 Register DstReg = MRI->createVirtualRegister(&SubRC); in getSubOperand64()
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| H A D | SIISelLowering.cpp | 4163 const TargetRegisterClass *SubRC = in EmitInstrWithCustomInserter() local
4166 MII, MRI, Src2, Src2RC, AMDGPU::sub0, SubRC); in EmitInstrWithCustomInserter()
4168 MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC); in EmitInstrWithCustomInserter()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 123 if (const auto *SubRC = TRI.getCommonSubClass( in constrainOperandRegClass() local
125 OpRC = SubRC; in constrainOperandRegClass()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 5842 const TargetRegisterClass *SubRC; in genAlternativeCodeSequence() local
5846 SubRC = &AArch64::GPR32spRegClass; in genAlternativeCodeSequence()
5852 SubRC = &AArch64::GPR64spRegClass; in genAlternativeCodeSequence()
5857 Register NewVR = MRI.createVirtualRegister(SubRC); in genAlternativeCodeSequence()
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