| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | InfoByHwMode.cpp | 120 SpillSize = R->getValueAsInt("SpillSize"); in RegSizeInfo()
125 return std::tie(RegSize, SpillSize, SpillAlignment) < in operator <()
126 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment); in operator <()
132 SpillSize <= I.SpillSize; in isSubClassOf()
136 OS << "[R=" << RegSize << ",S=" << SpillSize in writeToStream()
170 return std::tie(A0.SpillSize, A0.SpillAlignment) > in hasStricterSpillThan()
171 std::tie(B0.SpillSize, B0.SpillAlignment); in hasStricterSpillThan()
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| H A D | InfoByHwMode.h | 148 unsigned SpillSize; member
155 return std::tie(RegSize, SpillSize, SpillAlignment) ==
156 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
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| H A D | RegisterBankEmitter.cpp | 84 else if (RCWithLargestRegsSize->RSI.get(DefaultMode).SpillSize < in addRegisterClass()
85 RC->RSI.get(DefaultMode).SpillSize) in addRegisterClass()
245 unsigned Size = RC.RSI.get(DefaultMode).SpillSize; in emitBaseClassImplementation()
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| H A D | RegisterInfoEmitter.cpp | 1303 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
1736 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; in debugDump()
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| H A D | CodeGenRegisters.cpp | 796 RI.RegSize = RI.SpillSize = Size ? Size in CodeGenRegisterClass()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 239 unsigned RegSize, SpillSize, SpillAlignment; member
284 return getRegClassInfo(RC).SpillSize / 8; in getSpillSize()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | StatepointLowering.cpp | 115 unsigned SpillSize = ValueType.getStoreSize(); in allocateStackSlot() local
116 assert((SpillSize * 8) == in allocateStackSlot()
134 if (MFI.getObjectSize(FI) == SpillSize) { in allocateStackSlot()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | LiveDebugVariables.cpp | 1536 unsigned SpillSize; in rewriteLocations() local
1539 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize, in rewriteLocations()
1851 unsigned SpillSize, SpillOffset; in emitDebugValues() local
1861 TII->getStackSlotRange(TRC, SubReg, SpillSize, SpillOffset, *MF); in emitDebugValues()
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| H A D | TargetInstrInfo.cpp | 532 unsigned SpillSize; in foldPatchpoint() local
538 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); in foldPatchpoint()
542 MIB.addImm(SpillSize); in foldPatchpoint()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 1533 unsigned SpillSize = TRI->getSpillSize(*RC); in storeRegToStackSlot() local
1544 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize)); in storeRegToStackSlot()
1548 if (SrcReg.isVirtual() && SpillSize == 4) { in storeRegToStackSlot()
1563 unsigned Opcode = RI.isVectorSuperClass(RC) ? getAVSpillSaveOpcode(SpillSize) in storeRegToStackSlot()
1564 : RI.isAGPRClass(RC) ? getAGPRSpillSaveOpcode(SpillSize) in storeRegToStackSlot()
1565 : getVGPRSpillSaveOpcode(SpillSize); in storeRegToStackSlot()
1693 unsigned SpillSize = TRI->getSpillSize(*RC); in loadRegFromStackSlot() local
1710 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize)); in loadRegFromStackSlot()
1711 if (DestReg.isVirtual() && SpillSize == 4) { in loadRegFromStackSlot()
1727 ? getAVSpillRestoreOpcode(SpillSize) in loadRegFromStackSlot()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 2034 const uint64_t SpillSize = 4; // Condition register is always 4 bytes. in determineCalleeSaves() local
2038 MFI.CreateFixedObject(SpillSize, SpillOffset, in determineCalleeSaves()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 6803 unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC); in getBroadcastOpcode() local
6804 assert((SpillSize == 64 || STI.hasVLX()) && in getBroadcastOpcode()
6810 switch (SpillSize) { in getBroadcastOpcode()
6818 switch (SpillSize) { in getBroadcastOpcode()
6826 switch (SpillSize) { in getBroadcastOpcode()
6834 switch (SpillSize) { in getBroadcastOpcode()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | Target.td | 60 int SpillSize = SS; // Spill slot size in bits.
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | WritingAnLLVMBackend.rst | 354 int SpillSize = 0;
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