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Searched refs:ShiftOpcode (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineShifts.cpp96 Instruction::BinaryOps ShiftOpcode = Sh0->getOpcode(); in reassociateShiftAmtsOfTwoSameDirectionShifts() local
142 BinaryOperator *NewShift = BinaryOperator::Create(ShiftOpcode, X, NewShAmt); in reassociateShiftAmtsOfTwoSameDirectionShifts()
148 if (ShiftOpcode == Instruction::BinaryOps::Shl) { in reassociateShiftAmtsOfTwoSameDirectionShifts()
340 Instruction::BinaryOps ShiftOpcode = I.getOpcode(); in foldShiftOfShiftedLogic() local
349 return match(V, m_BinOp(ShiftOpcode, m_Value(), m_Value())) && in foldShiftOfShiftedLogic()
365 Value *NewShift1 = Builder.CreateBinOp(ShiftOpcode, X, ShiftSumC); in foldShiftOfShiftedLogic()
366 Value *NewShift2 = Builder.CreateBinOp(ShiftOpcode, Y, I.getOperand(1)); in foldShiftOfShiftedLogic()
H A DInstCombineCompares.cpp1677 unsigned ShiftOpcode = Shift->getOpcode(); in foldICmpAndShift() local
1678 bool IsShl = ShiftOpcode == Instruction::Shl; in foldICmpAndShift()
1683 if (ShiftOpcode == Instruction::Shl) { in foldICmpAndShift()
1694 } else if (ShiftOpcode == Instruction::LShr) { in foldICmpAndShift()
1707 assert(ShiftOpcode == Instruction::AShr && "Unknown shift opcode"); in foldICmpAndShift()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1496 unsigned ShiftOpcode = MI.getOpcode(); in matchShiftOfShiftedLogic() local
1497 assert((ShiftOpcode == TargetOpcode::G_SHL || in matchShiftOfShiftedLogic()
1498 ShiftOpcode == TargetOpcode::G_ASHR || in matchShiftOfShiftedLogic()
1499 ShiftOpcode == TargetOpcode::G_LSHR || in matchShiftOfShiftedLogic()
1500 ShiftOpcode == TargetOpcode::G_USHLSAT || in matchShiftOfShiftedLogic()
1501 ShiftOpcode == TargetOpcode::G_SSHLSAT) && in matchShiftOfShiftedLogic()
1525 if (MI->getOpcode() != ShiftOpcode || in matchShiftOfShiftedLogic()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp5621 unsigned ShiftOpcode = ISD::DELETED_NODE; in Select() local
5637 ShiftOpcode = X86::SHR64ri; in Select()
5645 ShiftOpcode = X86::SHL64ri; in Select()
5654 ShiftOpcode = X86::SHR64ri; in Select()
5660 ShiftOpcode = X86::SHR64ri; in Select()
5666 ShiftOpcode = X86::SHR64ri; in Select()
5673 if (ShiftOpcode != ISD::DELETED_NODE) { in Select()
5676 CurDAG->getMachineNode(ShiftOpcode, dl, MVT::i64, MVT::i32, in Select()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2364 unsigned ShiftOpcode = Op.getOpcode(); in unrollVectorShift() local
2374 if (ShiftOpcode == ISD::SRA) in unrollVectorShift()
2378 DAG.getNode(ShiftOpcode, DL, MVT::i32, ShiftedValue, MaskedShiftValue)); in unrollVectorShift()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp6110 unsigned ShiftOpcode = ShiftOp.getOpcode(); in foldLogicOfShifts() local
6112 !(ShiftOpcode == ISD::SHL || ShiftOpcode == ISD::SRL || in foldLogicOfShifts()
6113 ShiftOpcode == ISD::SRA)) in foldLogicOfShifts()
6123 if (LogicOp.getOperand(0).getOpcode() == ShiftOpcode && in foldLogicOfShifts()
6127 } else if (LogicOp.getOperand(1).getOpcode() == ShiftOpcode && in foldLogicOfShifts()
6138 SDValue NewShift = DAG.getNode(ShiftOpcode, DL, VT, LogicX, Y); in foldLogicOfShifts()
8633 unsigned ShiftOpcode = Shift->getOpcode(); in combineShiftOfShiftedLogic() local
8640 if (V.getOpcode() != ShiftOpcode || !V.hasOneUse()) in combineShiftOfShiftedLogic()
8679 SDValue NewShift2 = DAG.getNode(ShiftOpcode, DL, VT, Y, C1); in combineShiftOfShiftedLogic()
11838 auto ShiftOpcode = in foldExtendedSignBitTest() local
[all …]
H A DTargetLowering.cpp2130 unsigned ShiftOpcode = NLZ > NTZ ? ISD::SRL : ISD::SHL; in SimplifyDemandedBits() local
2131 if (!TLO.LegalOperations() || isOperationLegal(ShiftOpcode, VT)) { in SimplifyDemandedBits()
2135 SDValue NewOp = TLO.DAG.getNode(ShiftOpcode, dl, VT, Src, ShAmt); in SimplifyDemandedBits()