| /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 108 int ShiftAmount = 0; in generateInstSeqImpl() local
113 ShiftAmount = findFirstSet((uint64_t)Val); in generateInstSeqImpl()
114 Val >>= ShiftAmount; in generateInstSeqImpl()
118 if (ShiftAmount > 12 && !isInt<12>(Val)) { in generateInstSeqImpl()
121 ShiftAmount -= 12; in generateInstSeqImpl()
127 ShiftAmount -= 12; in generateInstSeqImpl()
146 if (ShiftAmount) { in generateInstSeqImpl()
148 Res.push_back(RISCVMatInt::Inst(RISCV::SLLI_UW, ShiftAmount)); in generateInstSeqImpl()
150 Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount)); in generateInstSeqImpl()
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| /llvm-project-15.0.7/llvm/include/llvm/Support/ |
| H A D | DivisionByConstantInfo.h | 24 unsigned ShiftAmount; ///< shift amount member
33 unsigned ShiftAmount; ///< shift amount member
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 320 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
324 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
338 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) { in LowerShifts()
343 ShiftAmount -= 4; in LowerShifts()
350 ShiftAmount -= 4; in LowerShifts()
355 ShiftAmount = 0; in LowerShifts()
360 ShiftAmount = 0; in LowerShifts()
365 ShiftAmount = 0; in LowerShifts()
370 ShiftAmount = 0; in LowerShifts()
394 if (4 <= ShiftAmount && ShiftAmount < 8) in LowerShifts()
[all …]
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| H A D | AVRShiftExpand.cpp | 92 Value *ShiftAmount = Builder.CreateTrunc(BI->getOperand(1), Int8Ty); in expand() local
96 Value *Cmp1 = Builder.CreateICmpEQ(ShiftAmount, Int8Zero); in expand()
103 ShiftAmountPHI->addIncoming(ShiftAmount, BB); in expand()
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| /llvm-project-15.0.7/llvm/lib/Support/ |
| H A D | DivisionByConstantInfo.cpp | 55 Retval.ShiftAmount = P - D.getBitWidth(); // resulting shift in get()
105 Retval.ShiftAmount = P - D.getBitWidth(); // resulting shift in get()
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/MCTargetDesc/ |
| H A D | SPIRVBaseInfo.h | 739 for (unsigned ShiftAmount = 0; ShiftAmount < 32; ShiftAmount += 8) { in getSPIRVStringOperand() local
740 char c = (Imm >> ShiftAmount) & 0xff; in getSPIRVStringOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYFrameLowering.cpp | 177 unsigned ShiftAmount = Log2(MaxAlignment); in emitPrologue() local
184 .addImm(ShiftAmount); in emitPrologue()
187 .addImm(ShiftAmount); in emitPrologue()
194 .addImm(ShiftAmount); in emitPrologue()
197 .addImm(ShiftAmount); in emitPrologue()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 1853 uint32_t ShiftAmount = Log2_32(NumOfVReg); in getVLENFactoredAmount() local
1854 if (ShiftAmount == 0) in getVLENFactoredAmount()
1858 .addImm(ShiftAmount) in getVLENFactoredAmount()
1866 uint32_t ShiftAmount; in getVLENFactoredAmount() local
1869 ShiftAmount = Log2_64(NumOfVReg / 9); in getVLENFactoredAmount()
1872 ShiftAmount = Log2_64(NumOfVReg / 5); in getVLENFactoredAmount()
1875 ShiftAmount = Log2_64(NumOfVReg / 3); in getVLENFactoredAmount()
1879 if (ShiftAmount) in getVLENFactoredAmount()
1882 .addImm(ShiftAmount) in getVLENFactoredAmount()
1893 .addImm(ShiftAmount) in getVLENFactoredAmount()
[all …]
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| H A D | RISCVRegisterInfo.cpp | 280 uint32_t ShiftAmount = Log2_32(ZvlssegInfo->second); in eliminateFrameIndex() local
281 if (ShiftAmount != 0) in eliminateFrameIndex()
284 .addImm(ShiftAmount); in eliminateFrameIndex()
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| H A D | RISCVFrameLowering.cpp | 568 unsigned ShiftAmount = Log2(MaxAlignment); in emitPrologue() local
573 .addImm(ShiftAmount) in emitPrologue()
577 .addImm(ShiftAmount) in emitPrologue()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.h | 48 unsigned ShiftAmount) const;
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| H A D | MipsTargetStreamer.h | 145 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
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| H A D | MipsSEISelDAGToDAG.cpp | 283 unsigned ShiftAmount = 0) const { in selectAddrFrameIndexOffset() argument
286 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) { in selectAddrFrameIndexOffset()
297 const Align Alignment(1ULL << ShiftAmount); in selectAddrFrameIndexOffset()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 274 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL() argument
276 if (ShiftAmount >= 32) { in emitDSLL()
277 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
281 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
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| H A D | MipsMCCodeEmitter.h | 188 template <unsigned ShiftAmount = 0>
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| H A D | MipsMCCodeEmitter.cpp | 751 template <unsigned ShiftAmount>
762 OffBits >>= ShiftAmount; in getMemEncoding()
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 969 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
974 if (ShiftAmount >= 8) { in LowerShifts()
994 ShiftAmount -= 8; in LowerShifts()
997 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
1001 ShiftAmount -= 1; in LowerShifts()
1004 while (ShiftAmount--) in LowerShifts()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 414 unsigned ShiftAmount; member
586 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
904 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
1983 unsigned ShiftAmount = 0, in CreateReg() argument
1991 Op->Reg.ShiftExtend.Amount = ShiftAmount; in CreateReg()
2002 unsigned ShiftAmount = 0, in CreateVectorReg() argument
2091 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
3014 int64_t ShiftAmount = getTok().getIntVal(); in tryParseImmWithOptionalShift() local
3016 if (ShiftAmount < 0) { in tryParseImmWithOptionalShift()
3023 if (ShiftAmount == 0 && Imm != nullptr) { in tryParseImmWithOptionalShift()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 6935 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
6937 ShiftAmount = C->countTrailingZeros(); in setLimitsForBinOp()
6941 Upper = C->ashr(ShiftAmount) + 1; in setLimitsForBinOp()
6944 Lower = C->ashr(ShiftAmount); in setLimitsForBinOp()
6956 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
6958 ShiftAmount = C->countTrailingZeros(); in setLimitsForBinOp()
6959 Lower = C->lshr(ShiftAmount); in setLimitsForBinOp()
6973 unsigned ShiftAmount = C->countLeadingOnes() - 1; in setLimitsForBinOp() local
6974 Lower = C->shl(ShiftAmount); in setLimitsForBinOp()
6978 unsigned ShiftAmount = C->countLeadingZeros() - 1; in setLimitsForBinOp() local
[all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 1047 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1049 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
1050 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
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| H A D | TargetLowering.cpp | 2133 unsigned ShiftAmount = NLZ > NTZ ? NLZ - NTZ : NTZ - NLZ; in SimplifyDemandedBits() local
5818 magics.ShiftAmount = 0; in BuildSDIV()
5972 assert(magics.ShiftAmount < Divisor.getBitWidth() && in BuildUDIV()
5974 PostShift = magics.ShiftAmount; in BuildUDIV()
5977 PostShift = magics.ShiftAmount - 1; in BuildUDIV()
7016 unsigned ShiftAmount = OuterBitSize - InnerBitSize; in expandMUL_LOHI() local
8243 SDValue ShiftAmount = in scalarizeVectorLoad() local
8328 SDValue ShiftAmount = in scalarizeVectorStore() local
8505 SDValue ShiftAmount = in expandUnalignedLoad() local
8619 SDValue ShiftAmount = DAG.getConstant( in expandUnalignedStore() local
[all …]
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| H A D | LegalizeIntegerTypes.cpp | 911 SDValue ShiftAmount = in PromoteIntRes_ADDSUBSHLSAT() local
914 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
917 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
921 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
3837 SDValue ShiftAmount = DAG.getShiftAmountConstant(Scale % NVTSize, NVT, dl); in ExpandIntRes_MULFIX() local
3839 ShiftAmount); in ExpandIntRes_MULFIX()
3841 ShiftAmount); in ExpandIntRes_MULFIX()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1861 uint64_t ShiftAmount = V.getConstantOperandVal(1); in factorOutPowerOf2() local
1862 if (ShiftAmount == Power) in factorOutPowerOf2()
1864 Ops[1] = CurDAG->getConstant(ShiftAmount - Power, in factorOutPowerOf2()
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCasts.cpp | 518 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt() local
520 if ((VecWidth % DestWidth != 0) || (ShiftAmount % DestWidth != 0)) in foldVecTruncToExtElt()
531 unsigned Elt = ShiftAmount / DestWidth; in foldVecTruncToExtElt()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 459 unsigned &ShiftAmount);
5274 const MCExpr *ShiftAmount; in parsePKHImm() local
5277 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parsePKHImm()
5281 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parsePKHImm()
5357 const MCExpr *ShiftAmount; in parseShifterImm() local
5359 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseShifterImm()
5363 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseShifterImm()
5419 const MCExpr *ShiftAmount; in parseRotImm() local
5421 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseRotImm()
5425 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseRotImm()
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