| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/ |
| H A D | legalize-ssubsat.mir | 16 ; CHECK-NEXT: [[SSUBO:%[0-9]+]]:_(s32), [[SSUBO1:%[0-9]+]]:_(s32) = G_SSUBO %x, %y
18 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SSUBO]], [[C]](s64)
23 ; CHECK-NEXT: %ssubsat:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[SSUBO]]
44 ; CHECK-NEXT: [[SSUBO:%[0-9]+]]:_(s64), [[SSUBO1:%[0-9]+]]:_(s32) = G_SSUBO %x, %y
46 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SSUBO]], [[C]](s64)
51 ; CHECK-NEXT: %ssubsat:_(s64) = G_SELECT [[AND]](s32), [[ADD]], [[SSUBO]]
|
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 327 SSUBO, enumerator
|
| H A D | SelectionDAGNodes.h | 3096 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
|
| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 119 setOperationAction(ISD::SSUBO, VT, Custom); in M68kTargetLowering()
1328 case ISD::SSUBO: in LowerOperation()
1401 case ISD::SSUBO: in LowerXALUO()
2115 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || in LowerSELECT()
2136 case ISD::SSUBO: in LowerSELECT()
2269 Cond.getOperand(0).getOpcode() == ISD::SSUBO || in LowerBRCOND()
2313 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO) { in LowerBRCOND()
2335 case ISD::SSUBO: in LowerBRCOND()
|
| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 100 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY, enumerator
|
| H A D | SystemZOperators.td | 276 def z_ssubo : SDNode<"SystemZISD::SSUBO", SDT_ZBinaryWithFlags>;
|
| H A D | SystemZISelDAGToDAG.cpp | 1350 case SystemZISD::SSUBO: in tryFoldLoadStoreIntoMemOperand()
|
| H A D | SystemZISelLowering.cpp | 181 setOperationAction(ISD::SSUBO, VT, Custom); in SystemZTargetLowering()
3966 case ISD::SSUBO: in lowerXALUO()
3967 BaseOp = SystemZISD::SSUBO; in lowerXALUO()
5738 case ISD::SSUBO: in LowerOperation()
5933 OPCODE(SSUBO); in getTargetNodeName()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 399 case ISD::SSUBO: in LegalizeOp()
834 case ISD::SSUBO: in Expand()
|
| H A D | SelectionDAGDumper.cpp | 309 case ISD::SSUBO: return "ssubo"; in getOperationName()
|
| H A D | LegalizeIntegerTypes.cpp | 179 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; in PromoteIntegerResult()
2514 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break; in ExpandIntegerResult()
3978 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) && in ExpandIntRes_SADDSUBO()
|
| H A D | LegalizeVectorTypes.cpp | 177 case ISD::SSUBO: in ScalarizeVectorResult()
1120 case ISD::SSUBO: in SplitVectorResult()
3782 case ISD::SSUBO: in WidenVectorResult()
|
| H A D | SelectionDAG.cpp | 3530 case ISD::SSUBO: in computeKnownBits()
4156 case ISD::SSUBO: in ComputeNumSignBits()
9071 case ISD::SSUBO: in getNode()
11165 Opcode == ISD::USUBO || Opcode == ISD::SSUBO || in UnrollVectorOverflowOp()
|
| H A D | DAGCombiner.cpp | 1685 case ISD::SSUBO: in visit()
3845 bool IsSigned = (ISD::SSUBO == N->getOpcode()); in visitSUBO()
3915 TLI.isOperationLegalOrCustom(ISD::SSUBO, N->getValueType(0))) in visitSSUBO_CARRY()
3916 return DAG.getNode(ISD::SSUBO, SDLoc(N), N->getVTList(), N0, N1); in visitSSUBO_CARRY()
|
| H A D | LegalizeDAG.cpp | 3495 case ISD::SSUBO: { in ExpandNode()
|
| H A D | TargetLowering.cpp | 8893 OverflowOp = ISD::SSUBO; in expandAddSubSat()
|
| H A D | SelectionDAGBuilder.cpp | 6820 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; in visitIntrinsicCall()
|
| /llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/ |
| H A D | LegalizerHelperTest.cpp | 1201 auto SSUBO = B.buildSSubo(S96, S1, Op0, Op1); in TEST_F() local
1207 Helper.narrowScalar(*SSUBO, 0, S32)); in TEST_F()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 814 setOperationAction({ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO, in initActions()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1552 setOperationAction(ISD::SSUBO, VT, Expand); in HexagonTargetLowering()
1629 ISD::UADDO, ISD::SSUBO, ISD::USUBO, ISD::SMUL_LOHI, ISD::UMUL_LOHI, in HexagonTargetLowering()
|
| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | xaluo.ll | 455 ; SSUBO
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1123 setOperationAction(ISD::SSUBO, MVT::i32, Custom); in ARMTargetLowering()
4900 case ISD::SSUBO: in getARMXALUOOp()
5084 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerSELECT()
5666 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerBRCOND()
5717 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerBR_CC()
10409 case ISD::SSUBO: in LowerOperation()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 559 setOperationAction(ISD::SSUBO, MVT::i32, Custom); in AArch64TargetLowering()
560 setOperationAction(ISD::SSUBO, MVT::i64, Custom); in AArch64TargetLowering()
3410 case ISD::SSUBO: in getAArch64XALUOOp()
5404 case ISD::SSUBO: in LowerOperation()
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2258 setOperationAction(ISD::SSUBO, VT, Custom); in X86TargetLowering()
23711 case ISD::SSUBO: in EmitTest()
24965 case ISD::SSUBO: in getX86XALUOOp()
25256 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || in LowerSELECT()
28927 DAG.getNode(Opcode == ISD::SADDSAT ? ISD::SADDO : ISD::SSUBO, DL, in LowerADDSAT_SUBSAT()
32326 case ISD::SSUBO: in LowerOperation()
|