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Searched refs:SINT_TO_FP (Results 1 – 25 of 42) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp681 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
767 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 }, in getCastInstrCost()
769 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 }, in getCastInstrCost()
771 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 }, in getCastInstrCost()
773 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 }, in getCastInstrCost()
775 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 }, in getCastInstrCost()
777 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 }, in getCastInstrCost()
779 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 }, in getCastInstrCost()
781 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 }, in getCastInstrCost()
783 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp173 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
178 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addTypeForNEON()
304 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addMVEVectorTypes()
456 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addMVEVectorTypes()
467 setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Expand); in addMVEVectorTypes()
5946 case ISD::SINT_TO_FP: in LowerVectorINT_TO_FP()
5948 Opc = ISD::SINT_TO_FP; in LowerVectorINT_TO_FP()
5966 if (Op.getOpcode() == ISD::SINT_TO_FP) in LowerINT_TO_FP()
9551 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
10354 case ISD::SINT_TO_FP: in LowerOperation()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1772 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, in getCastInstrCost()
1773 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, in getCastInstrCost()
1884 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, in getCastInstrCost()
1885 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
1886 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, in getCastInstrCost()
1887 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, in getCastInstrCost()
1888 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, in getCastInstrCost()
1889 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, in getCastInstrCost()
1890 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, in getCastInstrCost()
1891 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
[all …]
H A DREADME-FPStack.txt49 Add a target specific hook to DAG combiner to handle SINT_TO_FP and
H A DX86ISelLowering.cpp942 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in X86TargetLowering()
2361 ISD::SINT_TO_FP, in X86TargetLowering()
20670 assert((Op.getOpcode() == ISD::SINT_TO_FP || in LowerI64IntToFP_AVX512DQ()
20712 assert((Op.getOpcode() == ISD::SINT_TO_FP || in LowerI64IntToFP16()
20749 case ISD::SINT_TO_FP: in useVectorCast()
29574 if (Op->getOpcode() == ISD::SINT_TO_FP || in LowerWin64_INT128_TO_FP()
32949 case ISD::SINT_TO_FP: in ReplaceNodeResults()
52652 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P); in combineUIntToFP()
52699 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P); in combineSIntToFP()
54500 if (InOpcode == ISD::SINT_TO_FP && in combineEXTRACT_SUBVECTOR()
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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dpr23273.ll5 ; for SINT_TO_FP wrongly assumed that the target had at least SSE2.
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Ddagcombiner-bug-illegal-vec4-int-to-fp.ll7 ; ISD::UINT_TO_FP and ISD::SINT_TO_FP opcodes.
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1647 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
1648 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
1649 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
1655 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
1656 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
1657 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
1663 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
1664 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
1670 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
1679 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp470 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
471 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
472 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
1155 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1237 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1682 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForFixedLengthSVE()
5495 case ISD::SINT_TO_FP: in LowerOperation()
14537 (Opc != ISD::SINT_TO_FP && Opc != ISD::UINT_TO_FP)) in performFDivCombine()
14582 bool IsSigned = Opc == ISD::SINT_TO_FP; in performFDivCombine()
19524 case ISD::SINT_TO_FP: in PerformDAGCombine()
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/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def58 DAG_INSTRUCTION(SIToFP, 1, 1, experimental_constrained_sitofp, SINT_TO_FP)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h773 SINT_TO_FP, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp428 case ISD::SINT_TO_FP: in LegalizeOp()
544 case ISD::SINT_TO_FP: in Promote()
1351 if (((!IsStrict && TLI.getOperationAction(ISD::SINT_TO_FP, VT) == in ExpandUINT_TO_FLOAT()
1414 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), HI); in ExpandUINT_TO_FLOAT()
1416 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), LO); in ExpandUINT_TO_FLOAT()
H A DLegalizeDAG.cpp1002 case ISD::SINT_TO_FP: in LegalizeOp()
2322 Node->getOpcode() == ISD::SINT_TO_FP); in ExpandLegalINT_TO_FP()
2450 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Or); in ExpandLegalINT_TO_FP()
2452 Fast = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2475 Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2540 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP || in PromoteLegalINT_TO_FP()
2965 case ISD::SINT_TO_FP: in ExpandNode()
4245 case ISD::SINT_TO_FP: in ConvertNodeToLibcall()
4249 bool Signed = Node->getOpcode() == ISD::SINT_TO_FP || in ConvertNodeToLibcall()
4451 Node->getOpcode() == ISD::SINT_TO_FP || in PromoteNode()
[all …]
H A DLegalizeFloatTypes.cpp137 case ISD::SINT_TO_FP: in SoftenFloatResult()
769 bool Signed = N->getOpcode() == ISD::SINT_TO_FP || in SoftenFloatRes_XINT_TO_FP()
1273 case ISD::SINT_TO_FP: in ExpandFloatResult()
1671 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP || in ExpandFloatRes_XINT_TO_FP()
2298 case ISD::SINT_TO_FP: in PromoteFloatResult()
2661 case ISD::SINT_TO_FP: in SoftPromoteHalfResult()
H A DSelectionDAGDumper.cpp352 case ISD::SINT_TO_FP: return "sint_to_fp"; in getOperationName()
H A DFastISel.cpp310 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant()
1779 return selectCast(I, ISD::SINT_TO_FP); in selectOperator()
H A DLegalizeVectorTypes.cpp107 case ISD::SINT_TO_FP: in ScalarizeVectorResult()
646 case ISD::SINT_TO_FP: in ScalarizeVectorOperand()
1043 case ISD::SINT_TO_FP: in SplitVectorResult()
2726 case ISD::SINT_TO_FP: in SplitVectorOperand()
3817 case ISD::SINT_TO_FP: in WidenVectorResult()
5460 case ISD::SINT_TO_FP: in WidenVectorOperand()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp295 case ISD::SINT_TO_FP: in getCastInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp217 setOperationAction(ISD::SINT_TO_FP, T, Expand); in initializeHVXLowering()
222 setOperationAction(ISD::SINT_TO_FP, T, Custom); in initializeHVXLowering()
290 setOperationAction(ISD::SINT_TO_FP, T, Custom); in initializeHVXLowering()
2069 Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in LowerHvxConvertFpInt()
2403 case ISD::SINT_TO_FP: in LowerHvxOperation()
2473 case ISD::SINT_TO_FP: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1770 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1771 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1772 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp254 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
276 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
520 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
8356 if (UI->getOpcode() != ISD::SINT_TO_FP && in directMoveIsProfitable()
8369 bool IsSigned = Op.getOpcode() == ISD::SINT_TO_FP || in convertIntToFP()
8405 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP || in LowerINT_TO_FPDirectMove()
8495 bool IsSigned = Op.getOpcode() == ISD::SINT_TO_FP || in LowerINT_TO_FP()
14409 if (FirstInput.getOpcode() != ISD::SINT_TO_FP && in DAGCombineBuildVector()
14451 assert((N->getOpcode() == ISD::SINT_TO_FP || in combineFPToIntToFP()
14477 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; in combineFPToIntToFP()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp360 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
380 ISD::ROTR, ISD::SUB, ISD::SINT_TO_FP, in AMDGPUTargetLowering()
1168 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
1595 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
2388 (Signed && Subtarget->isGCN()) ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerINT_TO_FP32()
2425 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
2487 return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext); in LowerSINT_TO_FP()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1609 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1611 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
3141 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, in LowerOperation()
3513 case ISD::SINT_TO_FP: in ReplaceNodeResults()
3520 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp168 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
249 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}) in WebAssemblyTargetLowering()
1983 case ISD::SINT_TO_FP: in LowerConvertLow()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-split-fcvt.ll262 ; SINT_TO_FP

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