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Searched refs:SETULT (Results 1 – 25 of 55) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1438 SETULT, // 1 1 0 0 True if unordered or less than enumerator
1464 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAnalysis.cpp201 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
213 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
230 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
254 case ISD::SETULT: in getICmpCondCode()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td157 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
164 def : PatFPSetcc<SETULT, FCMP_CULT_S, FPR32>;
189 def : PatFPSelectcc<SETULT, FCMP_CULT_S, FSEL_S, FPR32>;
H A DLoongArchFloat64InstrInfo.td161 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
168 def : PatFPSetcc<SETULT, FCMP_CULT_D, FPR64>;
189 def : PatFPSelectcc<SETULT, FCMP_CULT_D, FSEL_D, FPR64>;
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp44 case ISD::SETULT: in intCondCode2Icc()
88 case ISD::SETULT: in fpCondCode2Fcc()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h120 case ISD::SETULT: in getRISCVCCForIntCC()
H A DRISCVInstrInfoVSDPatterns.td691 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
698 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
702 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
714 defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLEU", SETULT,
H A DRISCVInstrInfoVVLPatterns.td1067 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
1074 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
1078 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
1086 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
1090 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3310 case ISD::SETULT: { in get32BitZExtCompare()
3483 case ISD::SETULT: { in get32BitSExtCompare()
3639 case ISD::SETULT: { in get64BitZExtCompare()
3802 case ISD::SETULT: { in get64BitSExtCompare()
4057 case ISD::SETULT: in SelectCC()
4084 case ISD::SETULT: in SelectCC()
4145 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
4177 case ISD::SETULT: return 0; in getCRIdxForSetCC()
4199 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
4575 if (InnerCC == ISD::SETULT || InnerCC == ISD::SETUGT) { in mayUseP9Setb()
[all …]
H A DPPCInstrInfo.td3320 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3383 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3563 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3591 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3603 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3631 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3826 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3857 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3878 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
3900 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
[all …]
H A DPPCInstrSPE.td840 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
861 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp376 case ISD::SETULT: in softenSetCCOperands()
3777 if (Cond == ISD::CondCode::SETULT) { in optimizeSetCCOfSignedTruncationCheck()
3978 if (Cond == ISD::SETULT || Cond == ISD::SETUGT) { in simplifySetCCWithCTPOP()
3980 if (C1.ugt(CostLimit + (Cond == ISD::SETULT))) in simplifySetCCWithCTPOP()
3982 if (C1 == 0 && (Cond == ISD::SETULT)) in simplifySetCCWithCTPOP()
4372 case ISD::SETULT: in SimplifySetCC()
4395 case ISD::SETULT: in SimplifySetCC()
4611 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { in SimplifySetCC()
8848 case ISD::UMIN: CC = ISD::SETULT; break; in expandIntMINMAX()
9615 ISD::CondCode::SETULT); in expandFP_TO_INT_SAT()
[all …]
H A DLegalizeIntegerTypes.cpp2788 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
2858 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
2992 ISD::SETULT); in ExpandIntRes_ADDSUB()
3004 ISD::SETULT); in ExpandIntRes_ADDSUB()
3013 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
3086 Cond = ISD::SETULT; in ExpandIntRes_UADDSUBO()
3922 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT); in ExpandIntRes_MULFIX()
4798 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
4870 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
H A DSelectionDAGDumper.cpp458 case ISD::SETULT: return "setult"; in getOperationName()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp582 case ISD::SETULT: in NegateCC()
794 SET_NEWCC(SETULT, JULT); in EmitInstrWithCustomInserter()
H A DBPFInstrInfo.td101 [{return (N->getZExtValue() == ISD::SETULT);}]>;
121 [{return (N->getZExtValue() == ISD::SETULT);}]>;
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td77 defm LT_U : ComparisonInt<SETULT, "lt_u", 0x49, 0x54>;
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp48 case ISD::SETULT: in ISDCCtoARCCC()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp953 case ISD::SETULT: in isLegalDSPCondCode()
1758 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1764 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1847 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
H A DMipsMSAInstrInfo.td150 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
151 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
178 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
179 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
180 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
181 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
H A DMipsDSPInstrInfo.td1419 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1432 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td342 def COND_ULT : PatFrag<(ops), (OtherVT SETULT)>;
H A DR600ISelLowering.cpp88 ISD::SETUGT, ISD::SETULT, ISD::SETULE}, in R600TargetLowering()
91 setCondCodeAction({ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT}, in R600TargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp234 setCondCodeAction(ISD::SETULT, T, Expand); in initializeHVXLowering()
307 setCondCodeAction(ISD::SETULT, MVT::v64f16, Expand); in initializeHVXLowering()
320 setCondCodeAction(ISD::SETULT, MVT::v32f32, Expand); in initializeHVXLowering()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp561 case ISD::SETULT: in intCCToAVRCC()
686 CC = ISD::SETULT; in getAVRCmp()

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