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Searched refs:SETUGE (Results 1 – 25 of 55) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1437 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
1464 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAnalysis.cpp200 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
216 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
228 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
250 case ISD::SETUGE: in getICmpCondCode()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp50 case ISD::SETUGE: in intCondCode2Icc()
94 case ISD::SETUGE: in fpCondCode2Fcc()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h122 case ISD::SETUGE: in getRISCVCCForIntCC()
H A DRISCVInstrInfoVSDPatterns.td693 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
700 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
718 defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGTU", SETUGE,
H A DRISCVInstrInfoVVLPatterns.td1069 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
1076 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
1084 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
1094 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td83 defm GE_U : ComparisonInt<SETUGE, "ge_u", 0x4f, 0x5a>;
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td157 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
H A DLoongArchFloat64InstrInfo.td161 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
H A DLoongArchISelLowering.cpp69 ISD::SETUGT, ISD::SETUGE}; in LoongArchTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1345 case ISD::SETUGE: in combineFMinMaxLegacy()
1802 ISD::SETUGE); in LowerUDIVREM64()
1804 ISD::SETUGE); in LowerUDIVREM64()
1824 ISD::SETUGE); in LowerUDIVREM64()
1826 ISD::SETUGE); in LowerUDIVREM64()
1884 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE); in LowerUDIVREM64()
1890 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE); in LowerUDIVREM64()
1938 SDValue Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
1945 Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
H A DAMDGPUInstructions.td341 def COND_UGE : PatFrag<(ops), (OtherVT SETUGE)>;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3285 case ISD::SETUGE: in get32BitZExtCompare()
3458 case ISD::SETUGE: in get32BitSExtCompare()
3617 case ISD::SETUGE: in get64BitZExtCompare()
3780 case ISD::SETUGE: in get64BitSExtCompare()
4058 case ISD::SETUGE: in SelectCC()
4085 case ISD::SETUGE: in SelectCC()
4139 case ISD::SETUGE: in getPredicateForSetCC()
4164 case ISD::SETUGE: in getCRIdxForSetCC()
4198 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
4242 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
H A DPPCInstrInfo.td3360 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3644 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3661 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3673 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3690 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3703 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
3775 defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)),
3802 defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)),
3841 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
3867 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
[all …]
H A DPPCInstrSPE.td850 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
871 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp559 case ISD::SETUGE: in intCCToAVRCC()
673 CC = ISD::SETUGE; in getAVRCmp()
681 CC = ISD::SETUGE; in getAVRCmp()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp258 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in MipsSETargetLowering()
263 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); in MipsSETargetLowering()
359 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAIntType()
395 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAFloatType()
956 case ISD::SETUGE: return !IsV216; in isLegalDSPCondCode()
H A DMipsDSPInstrInfo.td1422 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1435 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td95 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
115 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
H A DBPFISelLowering.cpp790 SET_NEWCC(SETUGE, JUGE); in EmitInstrWithCustomInserter()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp457 case ISD::SETUGE: return "setuge"; in getOperationName()
H A DTargetLowering.cpp391 case ISD::SETUGE: in softenSetCCOperands()
3787 } else if (Cond == ISD::CondCode::SETUGE) { in optimizeSetCCOfSignedTruncationCheck()
4369 case ISD::SETUGE: in SimplifySetCC()
4394 case ISD::SETUGE: in SimplifySetCC()
4571 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
4723 (Cond == ISD::SETUGE && C1.isMinSignedValue())) in SimplifySetCC()
4799 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
4812 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
4861 case ISD::SETUEQ: NewCond = IsNegInf ? ISD::SETULE : ISD::SETUGE; break; in SimplifySetCC()
5023 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp46 case ISD::SETUGE: in ISDCCtoARCCC()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1511 case ISD::SETUGE: in TranslateIntegerM68kCC()
1561 case ISD::SETUGE: in TranslateM68kCC()
1590 case ISD::SETUGE: // flipped in TranslateM68kCC()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp233 setCondCodeAction(ISD::SETUGE, T, Expand); in initializeHVXLowering()
306 setCondCodeAction(ISD::SETUGE, MVT::v64f16, Expand); in initializeHVXLowering()
319 setCondCodeAction(ISD::SETUGE, MVT::v32f32, Expand); in initializeHVXLowering()

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