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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dunsupported-cc.ll30 ; CHECK: SETGE * T{{[0-9]}}.[[CHAN:[XYZW]]], KC0[2].Z, literal.x
44 ; CHECK-NEXT: SETGE {{\*? *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, {{literal\.[xy]}}
117 ; CHECK-NEXT: SETGE {{\*? *}}T{{[0-9]\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z
H A Dllvm.round.ll21 ; R600-DAG: SETGE
H A Dsetcc.ll145 ; R600: SETGE
172 ; R600: SETGE
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1446 SETGE, // 1 X 0 1 1 True if greater than or equal enumerator
1458 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp42 case ISD::SETGE: in intCondCode2Icc()
77 case ISD::SETGE: in fpCondCode2Fcc()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAnalysis.cpp216 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
227 case ICmpInst::ICMP_SGE: return ISD::SETGE; in getICmpCondCode()
248 case ISD::SETGE: in getICmpCondCode()
H A DTargetLoweringBase.cpp678 CCs[RTLIB::OGE_F32] = ISD::SETGE; in InitCmpLibcallCCs()
679 CCs[RTLIB::OGE_F64] = ISD::SETGE; in InitCmpLibcallCCs()
680 CCs[RTLIB::OGE_F128] = ISD::SETGE; in InitCmpLibcallCCs()
681 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; in InitCmpLibcallCCs()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h118 case ISD::SETGE: in getRISCVCCForIntCC()
H A DRISCVInstrInfoVSDPatterns.td692 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLE", SETLE, SETGE>;
699 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLE", SETLE, SETGE>;
716 defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGT", SETGE,
H A DRISCVInstrInfoVVLPatterns.td1068 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>;
1075 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>;
1083 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>;
1092 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGT", SETGE, SETLE,
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td366 defm : BRCond_Bin_F2<SETGE, "f2FCMPHS", BT32, MVC32>;
410 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETGE)), bb:$imm16),
412 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETGE)),
414 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETGE)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td346 defm : BRCond_Bin<SETGE, "FCMPHS", BT32, MVC32>;
386 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETGE)), bb:$imm16),
388 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETGE)),
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp789 SET_NEWCC(SETGE, JSGE); in EmitInstrWithCustomInserter()
803 CC == ISD::SETGE || in EmitInstrWithCustomInserter()
H A DBPFInstrInfo.td89 [{return (N->getZExtValue() == ISD::SETGE);}]>;
109 [{return (N->getZExtValue() == ISD::SETGE);}]>;
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td82 defm GE_S : ComparisonInt<SETGE, "ge_s", 0x4e, 0x59>;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td328 def COND_OGE : PatFrags<(ops), [(OtherVT SETOGE), (OtherVT SETGE)]>;
354 def COND_SGE : PatFrag<(ops), (OtherVT SETGE)>;
H A DR600Instructions.td751 0xA, "SETGE",
870 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
1723 def : CND_INT_f32 <CNDGE_INT, SETGE>;
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp555 case ISD::SETGE: in intCCToAVRCC()
612 CC = ISD::SETGE; in getAVRCmp()
637 CC = ISD::SETGE; in getAVRCmp()
656 CC = ISD::SETGE; in getAVRCmp()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1237 X86_INTRINSIC_DATA(sse_comige_ss, COMI, X86ISD::COMI, ISD::SETGE),
1254 X86_INTRINSIC_DATA(sse_ucomige_ss, COMI, X86ISD::UCOMI, ISD::SETGE),
1262 X86_INTRINSIC_DATA(sse2_comige_sd, COMI, X86ISD::COMI, ISD::SETGE),
1309 X86_INTRINSIC_DATA(sse2_ucomige_sd, COMI, X86ISD::UCOMI, ISD::SETGE),
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp201 { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE }, in MSP430TargetLowering()
207 { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE }, in MSP430TargetLowering()
1096 case ISD::SETGE: in EmitCMP()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3192 case ISD::SETGE: { in get32BitZExtCompare()
3376 case ISD::SETGE: { in get32BitSExtCompare()
3535 case ISD::SETGE: { in get64BitZExtCompare()
3694 case ISD::SETGE: { in get64BitSExtCompare()
4054 case ISD::SETGE: in SelectCC()
4081 case ISD::SETGE: in SelectCC()
4140 case ISD::SETGE: in getPredicateForSetCC()
4165 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE in getCRIdxForSetCC()
4194 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break; in getVCmpInst()
4226 case ISD::SETGE: in getVCmpInst()
[all …]
H A DPPCInstrInfo.td3358 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
3466 defm : ExtSetCCPat<SETGE,
3498 defm : ExtSetCCPat<SETGE,
3646 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
3663 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3675 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3692 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3705 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
3777 defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGE)),
3804 defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGE)),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp845 case ISD::SETGE: in IntCondCCodeToICC()
1275 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp464 case ISD::SETGE: return "setge"; in getOperationName()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp58 case ISD::SETGE: in ISDCCtoARCCC()

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