1; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck --check-prefixes=GCN,FUNC %s
2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCN,GFX89,FUNC %s
3; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCN,GFX89,GFX9,FUNC %s
4; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600,FUNC %s
5
6; FUNC-LABEL: {{^}}round_f32:
7; GCN-DAG: s_load_dword [[SX:s[0-9]+]]
8; GCN-DAG: s_brev_b32 [[K:s[0-9]+]], -2{{$}}
9; GCN-DAG: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[SX]]
10; GCN-DAG: v_sub_f32_e32 [[SUB:v[0-9]+]], [[SX]], [[TRUNC]]
11; GCN-DAG: v_mov_b32_e32 [[VX:v[0-9]+]], [[SX]]
12; GCN: v_bfi_b32 [[COPYSIGN:v[0-9]+]], [[K]], 1.0, [[VX]]
13; GCN: v_cmp_ge_f32_e64 vcc, |[[SUB]]|, 0.5
14; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, [[VX]]
15; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TRUNC]], [[SEL]]
16; GCN: buffer_store_dword [[RESULT]]
17
18; R600: TRUNC {{.*}}, [[ARG:KC[0-9]\[[0-9]+\]\.[XYZW]]]
19; R600-DAG: ADD  {{.*}},
20; R600-DAG: BFI_INT
21; R600-DAG: SETGE
22; R600-DAG: CNDE
23; R600-DAG: ADD
24define amdgpu_kernel void @round_f32(float addrspace(1)* %out, float %x) #0 {
25  %result = call float @llvm.round.f32(float %x) #1
26  store float %result, float addrspace(1)* %out
27  ret void
28}
29
30; The vector tests are really difficult to verify, since it can be hard to
31; predict how the scheduler will order the instructions.  We already have
32; a test for the scalar case, so the vector tests just check that the
33; compiler doesn't crash.
34
35; FUNC-LABEL: {{^}}round_v2f32:
36; GCN: s_endpgm
37; R600: CF_END
38define amdgpu_kernel void @round_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) #0 {
39  %result = call <2 x float> @llvm.round.v2f32(<2 x float> %in) #1
40  store <2 x float> %result, <2 x float> addrspace(1)* %out
41  ret void
42}
43
44; FUNC-LABEL: {{^}}round_v4f32:
45; GCN: s_endpgm
46; R600: CF_END
47define amdgpu_kernel void @round_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) #0 {
48  %result = call <4 x float> @llvm.round.v4f32(<4 x float> %in) #1
49  store <4 x float> %result, <4 x float> addrspace(1)* %out
50  ret void
51}
52
53; FUNC-LABEL: {{^}}round_v8f32:
54; GCN: s_endpgm
55; R600: CF_END
56define amdgpu_kernel void @round_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %in) #0 {
57  %result = call <8 x float> @llvm.round.v8f32(<8 x float> %in) #1
58  store <8 x float> %result, <8 x float> addrspace(1)* %out
59  ret void
60}
61
62; FUNC-LABEL: {{^}}round_f16:
63; GFX89-DAG: s_load_dword [[SX:s[0-9]+]]
64; GFX89-DAG: s_movk_i32 [[K:s[0-9]+]], 0x7fff{{$}}
65; GFX89-DAG: v_mov_b32_e32 [[VX:v[0-9]+]], [[SX]]
66; GFX89-DAG: v_mov_b32_e32 [[BFI_K:v[0-9]+]], 0x3c00
67; GFX89: v_bfi_b32 [[COPYSIGN:v[0-9]+]], [[K]], [[BFI_K]], [[VX]]
68
69; GFX89: v_trunc_f16_e32 [[TRUNC:v[0-9]+]], [[SX]]
70; GFX89: v_sub_f16_e32 [[SUB:v[0-9]+]], [[SX]], [[TRUNC]]
71; GFX89: v_cmp_ge_f16_e64 vcc, |[[SUB]]|, 0.5
72; GFX89: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, [[COPYSIGN]]
73; GFX89: v_add_f16_e32 [[RESULT:v[0-9]+]], [[TRUNC]], [[SEL]]
74; GFX89: buffer_store_short [[RESULT]]
75define amdgpu_kernel void @round_f16(half addrspace(1)* %out, i32 %x.arg) #0 {
76  %x.arg.trunc = trunc i32 %x.arg to i16
77  %x = bitcast i16 %x.arg.trunc to half
78  %result = call half @llvm.round.f16(half %x) #1
79  store half %result, half addrspace(1)* %out
80  ret void
81}
82
83; Should be scalarized
84; FUNC-LABEL: {{^}}round_v2f16:
85; GFX89-DAG: s_movk_i32 [[K:s[0-9]+]], 0x7fff{{$}}
86; GFX89-DAG: v_mov_b32_e32 [[BFI_K:v[0-9]+]], 0x3c00
87; GFX89: v_bfi_b32 [[COPYSIGN0:v[0-9]+]], [[K]], [[BFI_K]],
88; GFX89: v_bfi_b32 [[COPYSIGN1:v[0-9]+]], [[K]], [[BFI_K]],
89
90; GFX9: v_pack_b32_f16
91define amdgpu_kernel void @round_v2f16(<2 x half> addrspace(1)* %out, i32 %in.arg) #0 {
92  %in = bitcast i32 %in.arg to <2 x half>
93  %result = call <2 x half> @llvm.round.v2f16(<2 x half> %in)
94  store <2 x half> %result, <2 x half> addrspace(1)* %out
95  ret void
96}
97
98declare float @llvm.round.f32(float) #1
99declare <2 x float> @llvm.round.v2f32(<2 x float>) #1
100declare <4 x float> @llvm.round.v4f32(<4 x float>) #1
101declare <8 x float> @llvm.round.v8f32(<8 x float>) #1
102
103declare half @llvm.round.f16(half) #1
104declare <2 x half> @llvm.round.v2f16(<2 x half>) #1
105declare <4 x half> @llvm.round.v4f16(<4 x half>) #1
106declare <8 x half> @llvm.round.v8f16(<8 x half>) #1
107
108attributes #0 = { nounwind }
109attributes #1 = { nounwind readnone }
110