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Searched refs:SCALAR_TO_VECTOR (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dbitcast.ll3 ; PR23065: SCALAR_TO_VECTOR implies the top elements 1 to N-1 of the N-element vector are undefined.
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelDAGToDAG.cpp96 case ISD::SCALAR_TO_VECTOR: in Select()
H A DSIISelLowering.cpp256 case ISD::SCALAR_TO_VECTOR: in SITargetLowering()
286 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
300 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
314 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
328 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
342 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
525 case ISD::SCALAR_TO_VECTOR: in SITargetLowering()
742 ISD::SCALAR_TO_VECTOR, in SITargetLowering()
4682 case ISD::SCALAR_TO_VECTOR: in LowerOperation()
5814 if (VecBC.getOpcode() == ISD::SCALAR_TO_VECTOR) { in lowerEXTRACT_VECTOR_ELT()
[all …]
H A DAMDGPUISelDAGToDAG.cpp231 SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo); in matchLoadD16FromBuildVector()
491 assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts); in SelectBuildVector()
564 case ISD::SCALAR_TO_VECTOR: in Select()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h606 SCALAR_TO_VECTOR, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; in ScalarizeVectorResult()
291 ISD::SCALAR_TO_VECTOR, DL, OtherVT, SDValue(ScalarNode, OtherNo)); in ScalarizeVecRes_OverflowOp()
737 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op); in ScalarizeVecOp_UnaryOp()
754 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_UnaryOp_StrictFP()
820 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res); in ScalarizeVecOp_VSETCC()
866 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_STRICT_FP_ROUND()
895 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_STRICT_FP_EXTEND()
965 case ISD::SCALAR_TO_VECTOR: in SplitVectorResult()
1790 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) { in SplitVecRes_ScalarOp()
3666 case ISD::SCALAR_TO_VECTOR: in WidenVectorResult()
[all …]
H A DLegalizeDAG.cpp405 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
1823 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V); in ExpandBVWithShuffles()
1931 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); in ExpandBUILD_VECTOR()
1986 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); in ExpandBUILD_VECTOR()
1989 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); in ExpandBUILD_VECTOR()
3027 case ISD::SCALAR_TO_VECTOR: in ExpandNode()
5002 case ISD::SCALAR_TO_VECTOR: { in PromoteNode()
H A DSelectionDAGDumper.cpp295 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; in getOperationName()
H A DDAGCombiner.cpp1788 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N); in visit()
5338 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) && in hoistLogicOpWithSameOpcodeHands()
19619 if (CurVec.getOpcode() == ISD::SCALAR_TO_VECTOR && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
19780 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
19851 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
19992 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
21136 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitCONCAT_VECTORS()
22044 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) { in combineShuffleOfScalars()
22527 SDValue Insert = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, NewBO); in visitVECTOR_SHUFFLE()
22536 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && SplatIndex == 0) in visitVECTOR_SHUFFLE()
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H A DLegalizeIntegerTypes.cpp124 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerResult()
1642 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerOperand()
4705 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; in ExpandIntegerOperand()
H A DTargetLowering.cpp1129 case ISD::SCALAR_TO_VECTOR: { in SimplifyDemandedBits()
2850 case ISD::SCALAR_TO_VECTOR: { in SimplifyDemandedVectorElts()
H A DSelectionDAG.cpp3069 case ISD::SCALAR_TO_VECTOR: { in computeKnownBits()
5348 case ISD::SCALAR_TO_VECTOR: in getNode()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVECustomDAG.cpp257 case ISD::SCALAR_TO_VECTOR: in getIdiomaticVectorType()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2326 ISD::SCALAR_TO_VECTOR, in X86TargetLowering()
8084 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR && in getTargetShuffleAndZeroables()
8354 case ISD::SCALAR_TO_VECTOR: in getFauxShuffleMask()
8361 if (Opcode != ISD::SCALAR_TO_VECTOR) { in getFauxShuffleMask()
8413 if (Opcode == ISD::SCALAR_TO_VECTOR) { in getFauxShuffleMask()
8804 if (Opcode == ISD::SCALAR_TO_VECTOR) in getShuffleScalarElt()
9163 case ISD::SCALAR_TO_VECTOR: in findEltLoadSrc()
38230 V2.getOpcode() == ISD::SCALAR_TO_VECTOR && in combineX86ShuffleChain()
39919 if (Src.getOpcode() == ISD::SCALAR_TO_VECTOR) in combineTargetShuffle()
40129 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) { in combineTargetShuffle()
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H A DX86ISelDAGToDAG.cpp1195 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1197 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
H A DX86FastISel.cpp2642 InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR, in fastLowerIntrinsicCall()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dscalar_to_vector.ll189 ; Getting a SCALAR_TO_VECTOR seems to be tricky. These cases managed
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DREADME_ALTIVEC.txt56 We currently codegen SCALAR_TO_VECTOR as a store of the scalar to a 16-byte
H A DPPCISelLowering.cpp856 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); in PPCTargetLowering()
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
964 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
978 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in PPCTargetLowering()
981 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in PPCTargetLowering()
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal); in PPCTargetLowering()
2972 UI->getOpcode() != ISD::SCALAR_TO_VECTOR && in usePartialVectorLoads()
9077 if (InputLoad->getOpcode() == ISD::SCALAR_TO_VECTOR || in getNormalLoadInput()
14779 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR) in isScalarToVec()
14784 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR) in isScalarToVec()
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H A DPPCISelDAGToDAG.cpp5676 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR && in Select()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp381 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in SystemZTargetLowering()
500 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in SystemZTargetLowering()
501 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in SystemZTargetLowering()
5183 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value); in buildScalarToVector()
5446 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op)) in lowerBUILD_VECTOR()
5470 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) || in lowerVECTOR_SHUFFLE()
5642 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) || in lowerShift()
5793 case ISD::SCALAR_TO_VECTOR: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp336 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal); in addMVEVectorTypes()
401 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in addMVEVectorTypes()
447 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); in addMVEVectorTypes()
6002 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
6004 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); in LowerFCOPYSIGN()
7916 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); in LowerBUILD_VECTOR()
8708 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { in LowerVECTOR_SHUFFLE()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td691 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp5308 SDValue Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f32, Load); in LowerLOAD()
10479 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) in LowerVECTOR_SHUFFLE()
11244 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); in LowerBUILD_VECTOR()
11451 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op0); in LowerBUILD_VECTOR()
18788 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0)); in performSelectCombine()
18790 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1)); in performSelectCombine()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1643 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR, in HexagonTargetLowering()