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Searched refs:SADDSAT (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dirtranslator-sat.ll88 ; CHECK-NEXT: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[TRUNC]], [[TRUNC1]]
89 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SADDSAT]](s16)
104 ; CHECK-NEXT: [[SADDSAT:%[0-9]+]]:_(s32) = G_SADDSAT [[COPY]], [[COPY1]]
105 ; CHECK-NEXT: $vgpr0 = COPY [[SADDSAT]](s32)
123 ; CHECK-NEXT: [[SADDSAT:%[0-9]+]]:_(s64) = G_SADDSAT [[MV]], [[MV1]]
124 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](s64)
144 ; CHECK-NEXT: [[SADDSAT:%[0-9]+]]:_(<2 x s32>) = G_SADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
145 …; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](<2 x …
H A Dlegalize-saddsat.mir67 ; GFX9-NEXT: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL]], [[SHL1]]
68 ; GFX9-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT]], [[C]](s16)
139 ; GFX9-NEXT: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL]], [[SHL1]]
140 ; GFX9-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT]], [[C]](s16)
260 ; GFX9-NEXT: [[SADDSAT:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[SHL]], [[SHL1]]
337 ; GFX9-NEXT: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[TRUNC]], [[TRUNC1]]
338 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SADDSAT]](s16)
438 ; GFX9-NEXT: $vgpr0 = COPY [[SADDSAT]](<2 x s16>)
829 ; GFX9-NEXT: [[SADDSAT:%[0-9]+]]:_(s32) = G_SADDSAT [[COPY]], [[COPY1]]
830 ; GFX9-NEXT: $vgpr0 = COPY [[SADDSAT]](s32)
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h340 SADDSAT, enumerator
H A DTargetLowering.h2623 case ISD::SADDSAT: in isCommutativeBinOp()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2918 { ISD::SADDSAT, MVT::v32i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2919 { ISD::SADDSAT, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2993 { ISD::SADDSAT, MVT::v32i16, 2 }, in getTypeBasedIntrinsicInstrCost()
2994 { ISD::SADDSAT, MVT::v64i8, 2 }, in getTypeBasedIntrinsicInstrCost()
3064 { ISD::SADDSAT, MVT::v16i16, 1 }, in getTypeBasedIntrinsicInstrCost()
3065 { ISD::SADDSAT, MVT::v32i8, 1 }, in getTypeBasedIntrinsicInstrCost()
3119 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert in getTypeBasedIntrinsicInstrCost()
3120 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert in getTypeBasedIntrinsicInstrCost()
3231 { ISD::SADDSAT, MVT::v8i16, 1 }, in getTypeBasedIntrinsicInstrCost()
3232 { ISD::SADDSAT, MVT::v16i8, 1 }, in getTypeBasedIntrinsicInstrCost()
[all …]
H A DX86ISelLowering.cpp1058 setOperationAction(ISD::SADDSAT, MVT::v16i8, Legal); in X86TargetLowering()
1062 setOperationAction(ISD::SADDSAT, MVT::v8i16, Legal); in X86TargetLowering()
1254 setOperationAction(ISD::SADDSAT, MVT::v2i64, Custom); in X86TargetLowering()
1473 setOperationAction(ISD::SADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom); in X86TargetLowering()
1477 setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
1828 setOperationAction(ISD::SADDSAT, VT, HasBWI ? Legal : Custom); in X86TargetLowering()
28921 if ((Opcode == ISD::SADDSAT || Opcode == ISD::SSUBSAT) && in LowerADDSAT_SUBSAT()
28927 DAG.getNode(Opcode == ISD::SADDSAT ? ISD::SADDO : ISD::SSUBO, DL, in LowerADDSAT_SUBSAT()
32339 case ISD::SADDSAT: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp404 case ISD::SADDSAT: in LegalizeOp()
844 case ISD::SADDSAT: in Expand()
H A DSelectionDAGDumper.cpp321 case ISD::SADDSAT: return "saddsat"; in getOperationName()
H A DLegalizeIntegerTypes.cpp193 case ISD::SADDSAT: in PromoteIntegerResult()
897 case ISD::SADDSAT: in PromoteIntRes_ADDSUBSHLSAT()
924 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB; in PromoteIntRes_ADDSUBSHLSAT()
2520 case ISD::SADDSAT: in ExpandIntegerResult()
H A DLegalizeVectorTypes.cpp132 case ISD::SADDSAT: in ScalarizeVectorResult()
1090 case ISD::SADDSAT: in SplitVectorResult()
3716 case ISD::SADDSAT: in WidenVectorResult()
H A DSelectionDAG.cpp5449 case ISD::SADDSAT: return C1.sadd_sat(C2); in FoldValue()
5982 case ISD::SADDSAT: in getNode()
5991 if (Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT) in getNode()
6346 case ISD::SADDSAT: in getNode()
H A DLegalizeDAG.cpp1139 case ISD::SADDSAT: in LegalizeOp()
3415 case ISD::SADDSAT: in ExpandNode()
H A DTargetLowering.cpp8886 case ISD::SADDSAT: in expandAddSubSat()
9267 unsigned OpcSat = IsAdd ? ISD::SADDSAT : ISD::SSUBSAT; in expandSADDSUBO()
H A DSelectionDAGBuilder.cpp6524 setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2)); in visitIntrinsicCall()
H A DDAGCombiner.cpp1677 case ISD::SADDSAT: in visit()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp802 ISD::SADDSAT, ISD::UADDSAT, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp212 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in addTypeForNEON()
270 setOperationAction(ISD::SADDSAT, VT, Legal); in addMVEVectorTypes()
1129 setOperationAction(ISD::SADDSAT, MVT::i8, Custom); in ARMTargetLowering()
1131 setOperationAction(ISD::SADDSAT, MVT::i16, Custom); in ARMTargetLowering()
1139 setOperationAction(ISD::SADDSAT, MVT::i32, Legal); in ARMTargetLowering()
5039 case ISD::SADDSAT: in LowerADDSUBSAT()
5055 case ISD::SADDSAT: in LowerADDSUBSAT()
7755 case ISD::SADDSAT: in IsQRMVEInstruction()
10414 case ISD::SADDSAT: in LowerOperation()
10518 case ISD::SADDSAT: in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp179 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT}) in WebAssemblyTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp432 setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, {MVT::i16, MVT::i32}, in SITargetLowering()
636 ISD::UADDSAT, ISD::USUBSAT, ISD::SADDSAT, ISD::SSUBSAT}, in SITargetLowering()
655 ISD::UADDSAT, ISD::SADDSAT, ISD::USUBSAT, in SITargetLowering()
4739 case ISD::SADDSAT: in LowerOperation()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td422 def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp577 {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, VT, Legal); in RISCVTargetLowering()
837 {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, VT, in RISCVTargetLowering()
3548 case ISD::SADDSAT: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1038 setOperationAction(ISD::SADDSAT, VT, Legal); in AArch64TargetLowering()
1195 setOperationAction(ISD::SADDSAT, VT, Legal); in AArch64TargetLowering()
16637 return convertMergedOpToPredOp(N, ISD::SADDSAT, DAG, true); in performIntrinsicCombine()
16645 return DAG.getNode(ISD::SADDSAT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp755 setOperationAction(ISD::SADDSAT, VT, Legal); in PPCTargetLowering()