| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/ |
| H A D | legalize-saddsat.mir | 16 ; CHECK-NEXT: [[SADDO:%[0-9]+]]:_(s32), [[SADDO1:%[0-9]+]]:_(s32) = G_SADDO %x, %y 18 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SADDO]], [[C]](s64) 23 ; CHECK-NEXT: %saddsat:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[SADDO]] 44 ; CHECK-NEXT: [[SADDO:%[0-9]+]]:_(s64), [[SADDO1:%[0-9]+]]:_(s32) = G_SADDO %x, %y 46 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SADDO]], [[C]](s64) 51 ; CHECK-NEXT: %saddsat:_(s64) = G_SELECT [[AND]](s32), [[ADD]], [[SADDO]]
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 323 SADDO, enumerator
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| H A D | SelectionDAGNodes.h | 3096 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
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| H A D | TargetLowering.h | 2619 case ISD::SADDO: in isCommutativeBinOp()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 117 setOperationAction(ISD::SADDO, VT, Custom); in M68kTargetLowering() 1326 case ISD::SADDO: in LowerOperation() 1393 case ISD::SADDO: in LowerXALUO() 2116 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerSELECT() 2128 case ISD::SADDO: in LowerSELECT() 2267 (Cond.getOperand(0).getOpcode() == ISD::SADDO || in LowerBRCOND() 2312 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerBRCOND() 2327 case ISD::SADDO: in LowerBRCOND()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 100 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY, enumerator
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| H A D | SystemZOperators.td | 275 def z_saddo : SDNode<"SystemZISD::SADDO", SDT_ZBinaryWithFlags>;
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| H A D | SystemZISelDAGToDAG.cpp | 1353 case SystemZISD::SADDO: in tryFoldLoadStoreIntoMemOperand()
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| H A D | SystemZISelLowering.cpp | 180 setOperationAction(ISD::SADDO, VT, Custom); in SystemZTargetLowering() 3961 case ISD::SADDO: in lowerXALUO() 3962 BaseOp = SystemZISD::SADDO; in lowerXALUO() 5737 case ISD::SADDO: in LowerOperation() 5932 OPCODE(SADDO); in getTargetNodeName()
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| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | xaluo.ll | 9 ; SADDO reg, reg 102 ; SADDO reg, 1 | INC 195 ; SADDO reg, imm | imm, reg
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 397 case ISD::SADDO: in LegalizeOp() 833 case ISD::SADDO: in Expand()
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| H A D | SelectionDAGDumper.cpp | 307 case ISD::SADDO: return "saddo"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 178 case ISD::SADDO: in PromoteIntegerResult() 1109 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; in PromoteIntRes_SADDSUBO() 2513 case ISD::SADDO: in ExpandIntegerResult() 3978 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) && in ExpandIntRes_SADDSUBO() 3986 bool IsAdd = Node->getOpcode() == ISD::SADDO; in ExpandIntRes_SADDSUBO() 4006 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? in ExpandIntRes_SADDSUBO()
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| H A D | LegalizeVectorTypes.cpp | 175 case ISD::SADDO: in ScalarizeVectorResult() 1118 case ISD::SADDO: in SplitVectorResult() 3780 case ISD::SADDO: in WidenVectorResult()
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| H A D | SelectionDAG.cpp | 3558 case ISD::SADDO: in computeKnownBits() 4152 case ISD::SADDO: in ComputeNumSignBits() 9069 case ISD::SADDO: in getNode() 11164 assert((Opcode == ISD::UADDO || Opcode == ISD::SADDO || in UnrollVectorOverflowOp()
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| H A D | DAGCombiner.cpp | 1682 case ISD::SADDO: in visit() 2960 bool IsSigned = (ISD::SADDO == N->getOpcode()); in visitADDO() 3100 TLI.isOperationLegalOrCustom(ISD::SADDO, N->getValueType(0))) in visitSADDO_CARRY() 3101 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0, N1); in visitSADDO_CARRY() 3864 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0, in visitSUBO() 5002 return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, DL, in visitMULO()
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| H A D | TargetLowering.cpp | 8887 OverflowOp = ISD::SADDO; in expandAddSubSat() 9257 bool IsAdd = Node->getOpcode() == ISD::SADDO; in expandSADDSUBO()
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| H A D | LegalizeDAG.cpp | 3494 case ISD::SADDO: in ExpandNode()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 3287 { ISD::SADDO, MVT::i64, 1 }, in getTypeBasedIntrinsicInstrCost() 3308 { ISD::SADDO, MVT::i32, 1 }, in getTypeBasedIntrinsicInstrCost() 3309 { ISD::SADDO, MVT::i16, 1 }, in getTypeBasedIntrinsicInstrCost() 3310 { ISD::SADDO, MVT::i8, 1 }, in getTypeBasedIntrinsicInstrCost() 3379 ISD = ISD::SADDO; in getTypeBasedIntrinsicInstrCost()
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| H A D | X86ISelLowering.cpp | 2256 setOperationAction(ISD::SADDO, VT, Custom); in X86TargetLowering() 24957 case ISD::SADDO: in getX86XALUOOp() 25257 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerSELECT() 28927 DAG.getNode(Opcode == ISD::SADDSAT ? ISD::SADDO : ISD::SSUBO, DL, in LowerADDSAT_SUBSAT() 32324 case ISD::SADDO: in LowerOperation()
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| /llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/ |
| H A D | LegalizerHelperTest.cpp | 1164 auto SADDO = B.buildSAddo(S96, S1, Op0, Op1); in TEST_F() local 1170 Helper.narrowScalar(*SADDO, 0, S32)); in TEST_F()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 814 setOperationAction({ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO, in initActions()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1551 setOperationAction(ISD::SADDO, VT, Expand); in HexagonTargetLowering() 1628 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1121 setOperationAction(ISD::SADDO, MVT::i32, Custom); in ARMTargetLowering() 4886 case ISD::SADDO: in getARMXALUOOp() 5084 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerSELECT() 5666 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerBRCOND() 5717 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerBR_CC() 10408 case ISD::SADDO: in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 555 setOperationAction(ISD::SADDO, MVT::i32, Custom); in AArch64TargetLowering() 556 setOperationAction(ISD::SADDO, MVT::i64, Custom); in AArch64TargetLowering() 3402 case ISD::SADDO: in getAArch64XALUOOp() 5402 case ISD::SADDO: in LowerOperation()
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