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Searched refs:ResVT (Results 1 – 25 of 31) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVECustomDAG.h164 SDValue getNode(unsigned OC, ArrayRef<EVT> ResVT, ArrayRef<SDValue> OpV,
166 auto N = DAG.getNode(OC, DL, ResVT, OpV);
172 SDValue getNode(unsigned OC, EVT ResVT, ArrayRef<SDValue> OpV,
174 auto N = DAG.getNode(OC, DL, ResVT, OpV);
184 SDValue getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, SDValue StartV,
H A DVVPInstrPatternsVec.td598 RegisterClass ResRC, ValueType ResVT,
601 def : Pat <(ResVT (!cast<SDPatternOperator>("vvp_reduce_"#VVPRedOp)
609 def : Pat <(ResVT (!cast<SDPatternOperator>("vvp_reduce_"#VVPRedOp)
618 RegisterClass ResRC, ValueType ResVT,
620 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "or", "VROR">;
621 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "and", "VRAND">;
622 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "xor", "VRXOR">;
623 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "add", "VSUM"#SumSuffix>;
624 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "smax", "VRMAX"#MinMaxSuffix>;
H A DVECustomDAG.cpp562 SDValue VECustomDAG::getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, in getLegalReductionOpVVP() argument
576 return getNode(ScalarOC, ResVT, {StartV, ReductionResV}); in getLegalReductionOpVVP()
583 getNode(VVPOpcode, ResVT, {StartV, VectorV, Mask, AVL}, Flags)); in getLegalReductionOpVVP()
586 getNode(VVPOpcode, ResVT, {VectorV, Mask, AVL}, Flags)); in getLegalReductionOpVVP()
H A DVVPISelLowering.cpp345 MVT ResVT = splitVectorType(Op.getValue(0).getSimpleValueType()); in splitVectorOp() local
388 CDAG.getNode(Op.getOpcode(), ResVT, OpVec, Op->getFlags()); in splitVectorOp()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2478 EVT ResVT = N->getValueType(0); in performVectorExtendCombine() local
2479 if (ResVT == MVT::v8i16) { in performVectorExtendCombine()
2483 } else if (ResVT == MVT::v4i32) { in performVectorExtendCombine()
2487 } else if (ResVT == MVT::v2i64) { in performVectorExtendCombine()
2545 EVT ResVT; in performVectorTruncZeroCombine() local
2552 ResVT = MVT::v4i32; in performVectorTruncZeroCombine()
2556 ResVT = MVT::v4f32; in performVectorTruncZeroCombine()
2592 EVT ResVT; in performVectorTruncZeroCombine() local
2597 ResVT = MVT::v4i32; in performVectorTruncZeroCombine()
2600 ResVT = MVT::v4f32; in performVectorTruncZeroCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp263 EVT ResVT = N->getValueType(0); in ScalarizeVecRes_OverflowOp() local
1640 EVT ResVT = N->getValueType(0); in SplitVecRes_OverflowOp() local
2849 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE() local
2868 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE_SEQ() local
2894 EVT ResVT = N->getValueType(0); in SplitVecOp_VP_REDUCE() local
2918 EVT ResVT = N->getValueType(0); in SplitVecOp_UnaryOp() local
2977 EVT ResVT = N->getValueType(0); in SplitVecOp_INSERT_SUBVECTOR() local
3559 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_ROUND() local
3600 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_TO_XINT_SAT() local
4211 EVT ResVT = N->getValueType(0); in WidenVecRes_OverflowOp() local
[all …]
H A DLegalizeIntegerTypes.cpp303 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0() local
305 N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
2272 EVT ResVT = N->getValueType(0); in PromoteIntOp_VECREDUCE() local
2296 if (ResVT.bitsGE(EltVT)) in PromoteIntOp_VECREDUCE()
2297 return DAG.getNode(Opcode, SDLoc(N), ResVT, Op); in PromoteIntOp_VECREDUCE()
2302 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, Reduce); in PromoteIntOp_VECREDUCE()
5544 EVT ResVT = N->getValueType(0); in PromoteIntOp_CONCAT_VECTORS() local
5547 if (ResVT.isScalableVector()) { in PromoteIntOp_CONCAT_VECTORS()
5548 SDValue ResVec = DAG.getUNDEF(ResVT); in PromoteIntOp_CONCAT_VECTORS()
5553 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op, in PromoteIntOp_CONCAT_VECTORS()
H A DSelectionDAG.cpp1853 APInt One(ResVT.getScalarSizeInBits(), 1); in getStepVector()
1854 return getStepVector(DL, ResVT, One); in getStepVector()
1858 assert(ResVT.getScalarSizeInBits() == StepVal.getBitWidth()); in getStepVector()
1859 if (ResVT.isScalableVector()) in getStepVector()
1861 ISD::STEP_VECTOR, DL, ResVT, in getStepVector()
1865 for (uint64_t i = 0; i < ResVT.getVectorNumElements(); i++) in getStepVector()
1868 return getBuildVector(ResVT, DL, OpsStepConstants); in getStepVector()
11169 EVT ResVT = N->getValueType(0); in UnrollVectorOverflowOp() local
11171 EVT ResEltVT = ResVT.getVectorElementType(); in UnrollVectorOverflowOp()
11176 unsigned NE = ResVT.getVectorNumElements(); in UnrollVectorOverflowOp()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4924 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
4932 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
4933 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
4967 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
4968 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
5068 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
5070 if (ResVT.isVector()) { in ReplaceINTRINSIC_W_CHAIN()
5073 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceINTRINSIC_W_CHAIN()
5074 EVT EltVT = ResVT.getVectorElementType(); in ReplaceINTRINSIC_W_CHAIN()
5158 DAG.getBuildVector(ResVT, DL, ScalarRes); in ReplaceINTRINSIC_W_CHAIN()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1570 if (ResVT != MVT::nxv2i1 && ResVT != MVT::nxv4i1 && ResVT != MVT::nxv8i1 && in shouldExpandGetActiveLaneMask()
1571 ResVT != MVT::nxv16i1 && ResVT != MVT::v2i1 && ResVT != MVT::v4i1 && in shouldExpandGetActiveLaneMask()
1572 ResVT != MVT::v8i1 && ResVT != MVT::v16i1) in shouldExpandGetActiveLaneMask()
17276 EVT ResVT = N->getValueType(0); in performUzpCombine() local
17349 EVT ResVT = N->getValueType(0); in performGLD1Combine() local
18719 EVT ResVT = N->getValueType(0); in performVSelectCombine() local
18743 EVT ResVT = N->getValueType(0); in performSelectCombine() local
18748 if (ResVT.isScalableVector()) in performSelectCombine()
19776 EVT ResVT = N->getValueType(0); in PerformDAGCombine() local
21480 RdxVT = getPackedSVEVectorVT(ResVT); in LowerReductionToSVE()
[all …]
H A DAArch64ISelLowering.h674 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h325 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp16846 EVT ResVT = N->getValueType(0); in PerformVECREDUCE_ADDCombine() local
16921 if (ResVT != RetTy) in PerformVECREDUCE_ADDCombine()
16926 ResVT.getScalarSizeInBits()) in PerformVECREDUCE_ADDCombine()
16958 ResVT.getScalarSizeInBits()) in PerformVECREDUCE_ADDCombine()
17020 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
17023 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
17039 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
17042 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
17054 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
17057 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
[all …]
H A DARMTargetTransformInfo.cpp1685 EVT ResVT = TLI->getValueType(DL, ResTy); in getExtendedAddReductionCost() local
1687 if (ST->hasMVEIntegerOps() && ValVT.isSimple() && ResVT.isSimple()) { in getExtendedAddReductionCost()
1699 unsigned RevVTSize = ResVT.getSizeInBits(); in getExtendedAddReductionCost()
H A DARMISelLowering.h617 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3511 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
3518 SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(), in lowerBITCAST()
3525 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
3541 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
6050 SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT, in combineExtract() argument
6078 return DAG.getUNDEF(ResVT); in combineExtract()
6108 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract()
6110 if (VT != ResVT) { in combineExtract()
6112 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op); in combineExtract()
6148 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp11440 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
11442 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
11525 MVT ShiftVT = ResVT; in LowerCONCAT_VECTORSvXi1()
11542 SDValue Vec = Zeros ? DAG.getConstant(0, dl, ResVT) : DAG.getUNDEF(ResVT); in LowerCONCAT_VECTORSvXi1()
22342 MVT ResVT = MVT::v4i32; in LowerFP_TO_INT() local
22353 ResVT = MVT::v8i32; in LowerFP_TO_INT()
22383 MVT ResVT = VT; in LowerFP_TO_INT() local
22412 if (ResVT != VT) in LowerFP_TO_INT()
43311 EVT ResVT = in combineVPDPBUSDPattern() local
43314 DP = DAG.getBitcast(ResVT, DP); in combineVPDPBUSDPattern()
[all …]
H A DX86FastISel.cpp3561 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3562 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3563 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3568 Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt; in fastLowerCall()
H A DX86ISelLowering.h1363 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DX86ISelDAGToDAG.cpp4623 MVT ResVT = Setcc.getSimpleValueType(); in tryVPTESTM() local
4624 MVT MaskVT = ResVT; in tryVPTESTM()
4679 unsigned RegClass = TLI->getRegClassFor(ResVT)->getID(); in tryVPTESTM()
4682 dl, ResVT, SDValue(CNode, 0), RC); in tryVPTESTM()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp7893 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
7955 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7974 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7988 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
7991 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7998 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
14698 EVT ResVT = Val.getValueType(); in combineStoreFPToInt() local
14700 if (!isTypeLegal(ResVT)) in combineStoreFPToInt()
14708 if (ResVT == MVT::f128 && !Subtarget.hasP9Vector()) in combineStoreFPToInt()
14711 if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() || in combineStoreFPToInt()
[all …]
H A DPPCISelDAGToDAG.cpp4410 EVT ResVT = VecVT.changeVectorElementTypeToInteger(); in trySETCC() local
4412 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0); in trySETCC()
4414 ResVT, VCmp, VCmp); in trySETCC()
4418 CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS); in trySETCC()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h1570 EVT ResVT = getTLI()->getValueType(DL, RetTy, true); in getIntrinsicInstrCost() local
1575 if (!getTLI()->shouldExpandGetActiveLaneMask(ResVT, ArgType)) { in getIntrinsicInstrCost()
H A DSelectionDAG.h853 SDValue getStepVector(const SDLoc &DL, EVT ResVT, APInt StepVal);
857 SDValue getStepVector(const SDLoc &DL, EVT ResVT);
H A DTargetLowering.h3002 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument

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