16846   EVT ResVT = N->getValueType(0);  in PerformVECREDUCE_ADDCombine()  local
16851   if (ResVT == MVT::i32 && N0.getOpcode() == ISD::ADD &&  in PerformVECREDUCE_ADDCombine()
16854     SDValue Red0 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(0));  in PerformVECREDUCE_ADDCombine()
16855     SDValue Red1 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(1));  in PerformVECREDUCE_ADDCombine()
16856     return DAG.getNode(ISD::ADD, dl, ResVT, Red0, Red1);  in PerformVECREDUCE_ADDCombine()
16890     if (ResVT != RetTy || N0->getOpcode() != ExtendCode)  in PerformVECREDUCE_ADDCombine()
16899     if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT ||  in PerformVECREDUCE_ADDCombine()
16921     if (ResVT != RetTy)  in PerformVECREDUCE_ADDCombine()
16926             ResVT.getScalarSizeInBits())  in PerformVECREDUCE_ADDCombine()
16951     if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT ||  in PerformVECREDUCE_ADDCombine()
16958             ResVT.getScalarSizeInBits())  in PerformVECREDUCE_ADDCombine()
17010     return DAG.getNode(ARMISD::VMLAVs, dl, ResVT, A, B);  in PerformVECREDUCE_ADDCombine()
17012     return DAG.getNode(ARMISD::VMLAVu, dl, ResVT, A, B);  in PerformVECREDUCE_ADDCombine()
17020     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17023     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17028     return DAG.getNode(ARMISD::VMLAVps, dl, ResVT, A, B, Mask);  in PerformVECREDUCE_ADDCombine()
17031     return DAG.getNode(ARMISD::VMLAVpu, dl, ResVT, A, B, Mask);  in PerformVECREDUCE_ADDCombine()
17039     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17042     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17046     return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A);  in PerformVECREDUCE_ADDCombine()
17048     return DAG.getNode(ARMISD::VADDVu, dl, ResVT, A);  in PerformVECREDUCE_ADDCombine()
17054     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17057     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17061     return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask);  in PerformVECREDUCE_ADDCombine()
17063     return DAG.getNode(ARMISD::VADDVpu, dl, ResVT, A, Mask);  in PerformVECREDUCE_ADDCombine()
17069     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17072     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17090       return DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, Ext);  in PerformVECREDUCE_ADDCombine()
20931 bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,  in isExtractSubvectorCheap()  argument
20933   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))  in isExtractSubvectorCheap()
20936   return (Index == 0 || Index == ResVT.getVectorNumElements());  in isExtractSubvectorCheap()