| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenDAGPatterns.h | 702 ValueTypeByHwMode getType(unsigned ResNo) const { in getType() argument 703 return Types[ResNo].getValueTypeByHwMode(); in getType() 707 return Types[ResNo]; in getExtType() 709 TypeSetByHwMode &getExtType(unsigned ResNo) { return Types[ResNo]; } in getExtType() argument 710 void setType(unsigned ResNo, const TypeSetByHwMode &T) { Types[ResNo] = T; } in setType() argument 712 return Types[ResNo].getMachineValueType().SimpleTy; in getSimpleType() 715 bool hasConcreteType(unsigned ResNo) const { in hasConcreteType() argument 716 return Types[ResNo].isValueTypeByHwMode(false); in hasConcreteType() 719 return Types[ResNo].empty(); in isTypeCompletelyUnknown() 723 unsigned getResultIndex(unsigned ResNo) const { return ResultPerm[ResNo]; } in getResultIndex() argument [all …]
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| H A D | CodeGenDAGPatterns.cpp | 1616 unsigned &ResNo) { in getOperandNum() argument 1619 ResNo = OpNo; in getOperandNum() 1653 return NodeToApply->UpdateNodeType(ResNo, VVT, TP); in ApplyTypeConstraint() 1670 return (int)NodeToApply->UpdateNodeType(ResNo, in ApplyTypeConstraint() 1770 return UpdateNodeType(ResNo, MVT::iPTR, TP); in UpdateNodeTypeFromInst() 2288 assert(ResNo == 0 && "This node only has one result!"); in getImplicitType() 2307 assert(ResNo == 0 && "This node only has one result!"); in getImplicitType() 2581 for (unsigned ResNo = 0; ResNo != NumResultsToAdd; ++ResNo) in ApplyTypeConstraints() local 2582 MadeChange |= UpdateNodeTypeFromInst(ResNo, Inst.getResult(ResNo), TP); in ApplyTypeConstraints() 2587 unsigned ResNo = NumResultsToAdd; in ApplyTypeConstraints() local [all …]
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| H A D | DAGISelMatcherGen.cpp | 1080 for (unsigned ResNo = 0; ResNo < Pattern.getDstPattern()->getNumResults(); in EmitResultCode() local 1081 ++ResNo) { in EmitResultCode() 1082 Results[ResNo] = Ops[Pattern.getDstPattern()->getResultIndex(ResNo)]; in EmitResultCode()
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| H A D | DAGISelMatcher.h | 499 unsigned ResNo; variable 502 : Matcher(CheckType), Type(type), ResNo(resno) {} in CheckTypeMatcher() 505 unsigned getResNo() const { return ResNo; } in getResNo()
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| H A D | DAGISelMatcher.cpp | 183 << ResNo << '\n'; in printImpl()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeDbgValue.h | 50 return u.s.ResNo; in getResNo() 71 static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo) { in fromNode() argument 72 return SDDbgOperand(Node, ResNo); in fromNode() 106 unsigned ResNo; ///< Valid for expressions. member 116 u.s.ResNo = R; in SDDbgOperand()
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| H A D | LegalizeTypes.h | 298 void PromoteIntegerResult(SDNode *N, unsigned ResNo); 353 SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo); 425 void ExpandIntegerResult(SDNode *N, unsigned ResNo); 530 void SoftenFloatResult(SDNode *N, unsigned ResNo); 612 void ExpandFloatResult(SDNode *N, unsigned ResNo); 682 void PromoteFloatResult(SDNode *N, unsigned ResNo); 723 void SoftPromoteHalfResult(SDNode *N, unsigned ResNo); 769 void ScalarizeVectorResult(SDNode *N, unsigned ResNo); 841 void SplitVectorResult(SDNode *N, unsigned ResNo); 939 void WidenVectorResult(SDNode *N, unsigned ResNo); [all …]
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| H A D | LegalizeFloatTypes.cpp | 59 dbgs() << "SoftenFloatResult #" << ResNo << ": "; in SoftenFloatResult() 70 R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break; in SoftenFloatResult() 156 SetSoftenedFloat(SDValue(N, ResNo), R); in SoftenFloatResult() 219 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); in SoftenFloatRes_MERGE_VALUES() 1192 if (CustomLowerNode(N, N->getValueType(ResNo), true)) in ExpandFloatResult() 1198 dbgs() << "ExpandFloatResult #" << ResNo << ": "; in ExpandFloatResult() 1281 SetExpandedFloat(SDValue(N, ResNo), Lo, Hi); in ExpandFloatResult() 2232 if (CustomLowerNode(N, N->getValueType(ResNo), true)) { in PromoteFloatResult() 2244 dbgs() << "PromoteFloatResult #" << ResNo << ": "; in PromoteFloatResult() 2315 SetPromotedFloat(SDValue(N, ResNo), R); in PromoteFloatResult() [all …]
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| H A D | LegalizeTypesGeneric.cpp | 34 void DAGTypeLegalizer::ExpandRes_MERGE_VALUES(SDNode *N, unsigned ResNo, in ExpandRes_MERGE_VALUES() argument 36 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); in ExpandRes_MERGE_VALUES() 503 void DAGTypeLegalizer::SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo, in SplitRes_MERGE_VALUES() argument 505 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); in SplitRes_MERGE_VALUES()
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| H A D | InstrEmitter.h | 47 void EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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| H A D | LegalizeVectorTypes.cpp | 180 R = ScalarizeVecRes_OverflowOp(N, ResNo); in ScalarizeVectorResult() 196 SetScalarizedVector(SDValue(N, ResNo), R); in ScalarizeVectorResult() 285 unsigned OtherNo = 1 - ResNo; in ScalarizeVecRes_OverflowOp() 295 return SDValue(ScalarNode, ResNo); in ScalarizeVecRes_OverflowOp() 1663 Lo = SDValue(LoNode, ResNo); in SplitVecRes_OverflowOp() 1664 Hi = SDValue(HiNode, ResNo); in SplitVecRes_OverflowOp() 1667 unsigned OtherNo = 1 - ResNo; in SplitVecRes_OverflowOp() 3785 Res = WidenVecRes_OverflowOp(N, ResNo); in WidenVectorResult() 4217 if (ResNo == 0) { in WidenVecRes_OverflowOp() 4245 unsigned OtherNo = 1 - ResNo; in WidenVecRes_OverflowOp() [all …]
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| H A D | InstrEmitter.cpp | 85 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, in EmitCopyFromReg() argument 90 SDValue Op(Node, ResNo); in EmitCopyFromReg() 103 MVT VT = Node->getSimpleValueType(ResNo); in EmitCopyFromReg() 114 User->getOperand(2).getResNo() == ResNo) { in EmitCopyFromReg() 124 if (Op.getNode() != Node || Op.getResNo() != ResNo) in EmitCopyFromReg() 179 SDValue Op(Node, ResNo); in EmitCopyFromReg()
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| H A D | LegalizeIntegerTypes.cpp | 46 if (CustomLowerNode(N, N->getValueType(ResNo), true)) { in PromoteIntegerResult() 54 dbgs() << "PromoteIntegerResult #" << ResNo << ": "; in PromoteIntegerResult() 279 SetPromotedInteger(SDValue(N, ResNo), Res); in PromoteIntegerResult() 284 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); in PromoteIntRes_MERGE_VALUES() 328 if (ResNo == 1) { in PromoteIntRes_AtomicCmpSwap() 1097 if (ResNo == 1) in PromoteIntRes_SADDSUBO() 1414 if (ResNo == 1) in PromoteIntRes_UADDSUBO() 1445 if (ResNo == 1) in PromoteIntRes_ADDSUBCARRY() 1499 if (ResNo == 1) in PromoteIntRes_XMULO() 2385 if (CustomLowerNode(N, N->getValueType(ResNo), true)) in ExpandIntegerResult() [all …]
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| H A D | LegalizeTypes.cpp | 975 SDValue DAGTypeLegalizer::DisintegrateMERGE_VALUES(SDNode *N, unsigned ResNo) { in DisintegrateMERGE_VALUES() argument 977 if (i != ResNo) in DisintegrateMERGE_VALUES() 979 return SDValue(N->getOperand(ResNo)); in DisintegrateMERGE_VALUES()
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| H A D | ScheduleDAGSDNodes.cpp | 121 unsigned ResNo = User->getOperand(2).getResNo(); in CheckForPhysRegDependency() local 127 if (ResNo >= II.getNumDefs() && II.hasImplicitDefOfPhysReg(Reg)) in CheckForPhysRegDependency() 133 TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo)); in CheckForPhysRegDependency()
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| H A D | TargetLowering.cpp | 5298 unsigned ResNo = 0; // ResNo - The result number of the next output. in ParseConstraints() local 5325 getSimpleValueType(DL, STy->getElementType(ResNo)); in ParseConstraints() 5327 assert(ResNo == 0 && "Asm only has one result!"); in ParseConstraints() 5331 ++ResNo; in ParseConstraints()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGNodes.h | 149 unsigned getResNo() const { return ResNo; } 160 return Node == O.Node && ResNo == O.ResNo; 166 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo); 235 V.ResNo = -1U; 241 V.ResNo = -2U; 973 return ValueList[ResNo]; 1113 : Node(node), ResNo(resno) { 1117 assert((!Node || !ResNo || ResNo < Node->getNumValues()) && 1127 return Node->getValueType(ResNo); 1167 return !Node->hasAnyUseOfValue(ResNo); [all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 290 unsigned ResNo = 0; // ResNo - The result number of the next output. in lowerInlineAsm() local 327 TLI->getSimpleValueType(DL, STy->getElementType(ResNo)); in lowerInlineAsm() 329 assert(ResNo == 0 && "Asm only has one result!"); in lowerInlineAsm() 333 ++ResNo; in lowerInlineAsm()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 15281 unsigned ResNo = Op0.getResNo(); in PerformExtractEltToVMOVRRD() local 15291 V->getOperand(0).getResNo() == ResNo; in PerformExtractEltToVMOVRRD() 16229 unsigned ResNo = UI.getUse().getResNo(); in CombineVLDDUP() local 16231 if (ResNo == NumVecs) in CombineVLDDUP() 16234 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); in CombineVLDDUP()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 43996 unsigned ResNo = InputVector.getResNo(); in combineExtractVectorElt() local 43997 auto IsBoolExtract = [&BoolExtracts, &ResNo, &IsVar](SDNode *Use) { in combineExtractVectorElt() 43999 Use->getOperand(0).getResNo() == ResNo && in combineExtractVectorElt()
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