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Searched refs:RegisterRef (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRDFRegisters.h71 struct RegisterRef { struct
75 RegisterRef() = default; argument
118 bool alias(RegisterRef RA, RegisterRef RB) const { in alias() argument
138 RegisterRef mapTo(RegisterRef RR, unsigned R) const;
163 bool aliasRR(RegisterRef RA, RegisterRef RB) const;
164 bool aliasRM(RegisterRef RR, RegisterRef RM) const;
165 bool aliasMM(RegisterRef RM, RegisterRef RN) const;
182 static bool isCoverOf(RegisterRef RA, RegisterRef RB, in isCoverOf()
194 RegisterRef intersectWith(RegisterRef RR) const;
195 RegisterRef clearIn(RegisterRef RR) const;
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H A DRDFLiveness.h83 NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode*> RefA,
91 NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode*> RefA) {
95 NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode*> DefA,
98 NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode*> DefA) {
102 std::pair<NodeSet,bool> getAllReachingDefsRec(RegisterRef RefRR,
105 NodeAddr<RefNode*> getNearestAliasedRef(RegisterRef RefRR,
164 std::pair<NodeSet,bool> getAllReachingDefsRecImpl(RegisterRef RefRR,
H A DRDFGraph.h412 using RegisterSet = std::set<RegisterRef>;
518 RegisterRef getRegRef(const DataFlowGraph &G) const;
525 void setRegRef(RegisterRef RR, DataFlowGraph &G);
740 PackedRegisterRef pack(RegisterRef RR) { in pack()
743 PackedRegisterRef pack(RegisterRef RR) const { in pack()
746 RegisterRef unpack(PackedRegisterRef PR) const { in unpack()
747 return RegisterRef(PR.Reg, LMI.getLaneMaskForIndex(PR.MaskId)); in unpack()
750 RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const;
751 RegisterRef makeRegRef(const MachineOperand &Op) const;
822 RegisterRef RR, NodeAddr<BlockNode*> PredB,
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRDFRegisters.cpp120 if (MI != Reg && aliasMM(RegisterRef(Reg), RegisterRef(MI))) in getAliasSet()
130 if (aliasRM(RegisterRef(Reg), RegisterRef(MI))) in getAliasSet()
136 bool PhysicalRegisterInfo::aliasRR(RegisterRef RA, RegisterRef RB) const { in aliasRR()
167 bool PhysicalRegisterInfo::aliasRM(RegisterRef RR, RegisterRef RM) const { in aliasRM()
202 bool PhysicalRegisterInfo::aliasMM(RegisterRef RM, RegisterRef RN) const { in aliasMM()
230 RegisterRef PhysicalRegisterInfo::mapTo(RegisterRef RR, unsigned R) const { in mapTo()
310 RegisterRef RegisterAggr::intersectWith(RegisterRef RR) const { in intersectWith()
314 return RegisterRef(); in intersectWith()
320 RegisterRef RegisterAggr::clearIn(RegisterRef RR) const { in clearIn()
327 return RegisterRef(); in makeRegRef()
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H A DRDFLiveness.cpp147 RegisterRef RR = TA.Addr->getRegRef(DFG); in getAllReachingDefs()
444 RegisterRef DR = DA.Addr->getRegRef(DFG); in getAllReachedUses()
560 RegisterRef R(UI->first, I.second); in computePhiInfo()
656 using SubMap = std::unordered_map<RegisterRef, RegisterRef>; in computePhiInfo()
664 RegisterRef S = Mid.clearIn(RR); in computePhiInfo()
695 RegisterRef R(T.first); in computePhiInfo()
707 if (RegisterRef SS = ClearIn(RegisterRef(R.Reg, M), MidDefs, SM)) { in computePhiInfo()
866 std::vector<RegisterRef> LV; in computeLiveIns()
1047 RegisterRef LRef(LE.first); in traverse()
1095 RegisterRef T = RRs.clearIn(LRef); in traverse()
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H A DRDFGraph.cpp753 LR.insert(RegisterRef(R)); in getLandingPadLiveIns()
756 LR.insert(RegisterRef(R)); in getLandingPadLiveIns()
907 RegisterRef RR = *I; in build()
932 for (RegisterRef RR : EHRegs) { in build()
970 return RegisterRef(Reg); in makeRegRef()
1325 RegisterRef RR = makeRegRef(Op); in buildStmt()
1418 auto MaxCoverIn = [this] (RegisterRef RR, RegisterSet &RRs) -> RegisterRef { in buildPhis()
1419 for (RegisterRef I : RRs) in buildPhis()
1426 for (RegisterRef I : HasDF->second) in buildPhis()
1429 std::vector<RegisterRef> MaxRefs; in buildPhis()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp178 struct RegisterRef { struct in __anon5c30da9c0111::HexagonExpandCondsets
230 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
238 bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
586 RegisterRef RS = SO; in getCondTfrOpcode()
645 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR)) in genCondTfrFor()
692 RegisterRef RT(ST); in split()
803 RegisterRef RR = Op; in canMoveOver()
909 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN, in renameInRange()
958 RegisterRef RT(MS); in predicate()
1034 RegisterRef RD = MD; in predicate()
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H A DRDFCopy.cpp46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg()); in interpretAsCopy()
47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy()
88 NodeId CopyPropagation::getLocalReachingDef(RegisterRef RefRR, in getLocalReachingDef()
110 dbgs() << ' ' << Print<RegisterRef>(J.first, DFG) << '=' in run()
111 << Print<RegisterRef>(J.second, DFG); in run()
121 auto MinPhysReg = [this] (RegisterRef RR) -> unsigned { in run()
145 RegisterRef DR = DA.Addr->getRegRef(DFG); in run()
149 RegisterRef SR = FR->second; in run()
174 dbgs() << "Can replace " << Print<RegisterRef>(DR, DFG) in run()
175 << " with " << Print<RegisterRef>(SR, DFG) << " in " in run()
H A DHexagonBitSimplify.cpp246 BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH,
463 BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH, in parseRegSequence()
1095 bool usedBitsEqual(BitTracker::RegisterRef RD, BitTracker::RegisterRef RS);
1307 BitTracker::RegisterRef RS) { in usedBitsEqual()
1641 BitTracker::RegisterRef MR; in processBlock()
1719 BitTracker::RegisterRef SL, SH; in propagateRegCopy()
1793 BitTracker::RegisterRef &Rs, BitTracker::RegisterRef &Rt);
1920 BitTracker::RegisterRef &Rt) { in matchPackhl()
2053 BitTracker::RegisterRef Rs, Rt; in genPackhl()
2178 BitTracker::RegisterRef RS = Op; in genExtractLow()
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H A DBitTracker.h37 struct RegisterRef;
53 RegisterCell get(RegisterRef RR) const;
54 void put(RegisterRef RR, const RegisterCell &RC);
55 void subst(RegisterRef OldRR, RegisterRef NewRR);
141 struct BitTracker::RegisterRef { struct
142 RegisterRef(Register R = 0, unsigned S = 0) : Reg(R), Sub(S) {} in Reg() argument
143 RegisterRef(const MachineOperand &MO) in RegisterRef() argument
397 uint16_t getRegBitWidth(const RegisterRef &RR) const;
399 RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const;
400 void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const;
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H A DRDFCopy.h38 using EqualityMap = std::map<RegisterRef, RegisterRef>;
54 NodeId getLocalReachingDef(RegisterRef RefRR, NodeAddr<InstrNode*> IA);
H A DHexagonBlockRanges.cpp262 RegisterRef R, const MachineRegisterInfo &MRI, in expandToSubRegs()
292 std::map<RegisterRef,IndexType> LastDef, LastUse; in computeInitialLiveRanges()
303 auto closeRange = [&LastUse,&LastDef,&LiveMap] (RegisterRef R) -> void { in computeInitialLiveRanges()
323 RegisterRef R = { Op.getReg(), Op.getSubReg() }; in computeInitialLiveRanges()
339 RegisterRef R = { Op.getReg(), Op.getSubReg() }; in computeInitialLiveRanges()
364 RegisterRef R = { PR, 0 }; in computeInitialLiveRanges()
371 for (RegisterRef R : Defs) in computeInitialLiveRanges()
375 for (RegisterRef S : Defs) { in computeInitialLiveRanges()
384 for (RegisterRef S : Clobbers) { in computeInitialLiveRanges()
435 auto addDeadRanges = [&IndexMap,&LiveMap,&DeadMap] (RegisterRef R) -> void { in computeDeadMap()
H A DHexagonBlockRanges.h35 struct RegisterRef { struct
39 bool operator<(RegisterRef R) const {
43 using RegisterSet = std::set<RegisterRef>;
145 using RegToRangeMap = std::map<RegisterRef, RangeList>;
149 static RegisterSet expandToSubRegs(RegisterRef R,
H A DBitTracker.cpp725 RegisterRef RD = MI.getOperand(0); in evaluate()
727 RegisterRef RS = MI.getOperand(1); in evaluate()
729 RegisterRef RT = MI.getOperand(3); in evaluate()
744 RegisterRef RD = MI.getOperand(0); in evaluate()
745 RegisterRef RS = MI.getOperand(1); in evaluate()
804 RegisterRef DefRR(MD); in visitPHI()
825 RegisterRef RU = PI.getOperand(i); in visitPHI()
856 RegisterRef RU(MO); in visitNonBranch()
862 RegisterRef RD(P.first); in visitNonBranch()
874 RegisterRef RD(MO); in visitNonBranch()
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H A DHexagonBitTracker.h27 using RegisterRef = BitTracker::RegisterRef; member
H A DHexagonOptAddrMode.cpp169 RegisterRef OffsetRR; in canRemoveAddasl()
172 RegisterRef RR = UA.Addr->getRegRef(*DFG); in canRemoveAddasl()
218 RegisterRef UR = UN.Addr->getRegRef(*DFG); in allValidCandidates()
251 RegisterRef DR = DA.Addr->getRegRef(*DFG); in getAllRealUses()
271 if (!DFG->getPRI().alias(RegisterRef(I.first), DR)) in getAllRealUses()
289 RegisterRef LRExtRR; in isSafeToExtLR()
294 RegisterRef RR = UA.Addr->getRegRef(*DFG); in isSafeToExtLR()
458 RegisterRef RR = UA.Addr->getRegRef(*DFG); in processAddUses()
H A DHexagonBitTracker.cpp94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); in mask()
161 std::vector<BT::RegisterRef> Vector;
168 Vector[i] = BT::RegisterRef(MO); in RegisterRefs()
176 const BT::RegisterRef &operator[](unsigned n) const { in operator []()
968 BT::RegisterRef PD(DefR, 0); in evaluate()
1023 RegisterRef PR = BI.getOperand(0); in evaluate()
1194 RegisterRef RD = MD; in evaluateLoad()
1223 RegisterRef RD = MI.getOperand(0); in evaluateFormalCopy()
1224 RegisterRef RS = MI.getOperand(1); in evaluateFormalCopy()
H A DHexagonRDFOpt.cpp113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonFrameLowering.cpp2460 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(), in optimizeSpillSlots()
2529 HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 }; in optimizeSpillSlots()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86LoadValueInjectionLoadHardening.cpp371 RegisterRef DefReg = Def.Addr->getRegRef(DFG); in getGadgetGraph()
377 if (DFG.getPRI().alias(RegisterRef(I.first), DefReg)) { in getGadgetGraph()