178     struct RegisterRef {  struct in __anon5c30da9c0111::HexagonExpandCondsets
179       RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),  in RegisterRef()  function
181       RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}  in RegisterRef()  argument
183       bool operator== (RegisterRef RR) const {  in operator ==()  argument
186       bool operator!= (RegisterRef RR) const { return !operator==(RR); }  in operator !=()  argument
187       bool operator< (RegisterRef RR) const {  in operator <()  argument
203     void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
204     bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
222     MachineInstr *getReachingDefForPred(RegisterRef RD,
230     void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
236     bool isIntReg(RegisterRef RR, unsigned &BW);
238     bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
295 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,  in addRefToMap()
305 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,  in isRefInMap()
470   std::set<RegisterRef> DefRegs;  in updateDeadsInRange()
497     std::map<RegisterRef,unsigned> ImpUses;  in updateDeadsInRange()
520     for (std::pair<RegisterRef, unsigned> P : ImpUses) {  in updateDeadsInRange()
521       RegisterRef R = P.first;  in updateDeadsInRange()
586     RegisterRef RS = SO;  in getCondTfrOpcode()
645     if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR))  in genCondTfrFor()
692     RegisterRef RT(ST);  in split()
693     if (RT == RegisterRef(SF)) {  in split()
746 MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,  in getReachingDefForPred()
769       RegisterRef RR = Op;  in getReachingDefForPred()
803     RegisterRef RR = Op;  in canMoveOver()
909 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,  in renameInRange()
923       if (!Op.isReg() || RO != RegisterRef(Op))  in renameInRange()
958   RegisterRef RT(MS);  in predicate()
1003       RegisterRef RR = Op;  in predicate()
1034   RegisterRef RD = MD;  in predicate()
1080         if (RegisterRef(MI.getOperand(0)) == RegisterRef(MI.getOperand(2))) {  in predicateInBlock()
1093 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {  in isIntReg()
1120 bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {  in coalesceRegisters()
1200     RegisterRef RD = CI->getOperand(0);  in coalesceSegments()
1201     RegisterRef RP = CI->getOperand(1);  in coalesceSegments()
1223       RegisterRef RS = S1;  in coalesceSegments()
1226         Done = coalesceRegisters(RD, RegisterRef(S1));  in coalesceSegments()
1234       RegisterRef RS = S2;  in coalesceSegments()
1237         Done = coalesceRegisters(RD, RegisterRef(S2));  in coalesceSegments()