| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ResourcePriorityQueue.cpp | 56 RegPressure.resize(NumRC); in ResourcePriorityQueue()
58 std::fill(RegPressure.begin(), RegPressure.end(), 0); in ResourcePriorityQueue()
364 if ((RegPressure[RC->getID()] + in regPressureDelta()
366 (RegPressure[RC->getID()] + in regPressureDelta()
479 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID()); in scheduledNode()
490 if (RegPressure[RC->getID()] > in scheduledNode()
492 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID()); in scheduledNode()
493 else RegPressure[RC->getID()] = 0; in scheduledNode()
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| H A D | ScheduleDAGRRList.cpp | 1758 std::vector<unsigned> RegPressure; member in __anon4c419b9e0311::RegReductionPQBase
1777 RegPressure.resize(NumRC); in RegReductionPQBase()
1779 std::fill(RegPressure.begin(), RegPressure.end(), 0); in RegReductionPQBase()
1802 std::fill(RegPressure.begin(), RegPressure.end(), 0); in releaseState()
2091 unsigned RP = RegPressure[Id]; in dumpRegPressure()
2136 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
2228 RegPressure[RCId] += Cost; in scheduledNode()
2243 if (RegPressure[RCId] < Cost) { in scheduledNode()
2248 RegPressure[RCId] = 0; in scheduledNode()
2251 RegPressure[RCId] -= Cost; in scheduledNode()
[all …]
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| H A D | SelectionDAGISel.cpp | 264 if (TLI->getSchedulingPreference() == Sched::RegPressure) in createDefaultScheduler()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineLICM.cpp | 145 SmallVector<unsigned, 8> RegPressure; member in __anonfbf8dede0111::MachineLICMBase
186 RegPressure.clear(); in releaseMemory()
355 RegPressure.resize(NumRPS); in runOnMachineFunction()
356 std::fill(RegPressure.begin(), RegPressure.end(), 0); in runOnMachineFunction()
685 BackTrace.push_back(RegPressure); in EnterScope()
800 std::fill(RegPressure.begin(), RegPressure.end(), 0); in InitRegPressure()
823 if (static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second) in UpdateRegPressure()
824 RegPressure[Class] = 0; in UpdateRegPressure()
826 RegPressure[Class] += RPIdAndCost.second; in UpdateRegPressure()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ResourcePriorityQueue.h | 52 std::vector<unsigned> RegPressure; variable
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| H A D | MachineScheduler.h | 414 IntervalPressure RegPressure; variable
434 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure), in ScheduleDAGMILive()
454 const IntervalPressure &getRegPressure() const { return RegPressure; } in getRegPressure()
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| H A D | TargetLowering.h | 100 RegPressure, // Scheduling for lowest register pressure. enumerator
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| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | sched-assert-onlydbg-value-empty-region.mir | 5 # instructions. The RegPressure tracker would end up skipping over any
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 48 setSchedulingPreference(Sched::RegPressure); in AVRTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 55 setSchedulingPreference(Sched::RegPressure); in WebAssemblyTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 385 setSchedulingPreference(Sched::RegPressure); in NVPTXTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1584 setSchedulingPreference(Sched::RegPressure); in ARMTargetLowering()
1942 return Sched::RegPressure; in getSchedulingPreference()
1953 return Sched::RegPressure; in getSchedulingPreference()
1961 return Sched::RegPressure; in getSchedulingPreference()
1966 return Sched::RegPressure; in getSchedulingPreference()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 432 setSchedulingPreference(Sched::RegPressure); in AMDGPUTargetLowering()
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| H A D | SIISelLowering.cpp | 774 setSchedulingPreference(Sched::RegPressure); in SITargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 126 setSchedulingPreference(Sched::RegPressure); in SystemZTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 128 setSchedulingPreference(Sched::RegPressure); in X86TargetLowering()
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