| /llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiInstPrinter.cpp | 214 const MCOperand &RegOp) { in printMemoryBaseRegister() argument
215 assert(RegOp.isReg() && "Register operand expected"); in printMemoryBaseRegister()
219 OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg()); in printMemoryBaseRegister()
240 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand() local
249 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemRiOperand()
255 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRrOperand() local
259 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected."); in printMemRrOperand()
265 OS << "%" << getRegisterName(RegOp.getReg()); in printMemRrOperand()
276 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemSplsOperand() local
285 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemSplsOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVDuplicatesTracker.cpp | 56 MachineOperand *RegOp = &MRI.getVRegDef(Op.getReg())->getOperand(0); in buildDepsGraph() local
58 Reg2Entry.count(RegOp)); in buildDepsGraph()
59 if (Reg2Entry.count(RegOp)) in buildDepsGraph()
60 E->addDep(Reg2Entry[RegOp]); in buildDepsGraph()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 528 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState() argument
529 assert(RegOp.isReg() && "Not a register operand"); in getRegState()
530 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | in getRegState()
531 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) | in getRegState()
532 getUndefRegState(RegOp.isUndef()) | in getRegState()
533 getInternalReadRegState(RegOp.isInternalRead()) | in getRegState()
534 getDebugRegState(RegOp.isDebug()) | in getRegState()
535 getRenamableRegState(Register::isPhysicalRegister(RegOp.getReg()) && in getRegState()
536 RegOp.isRenamable()); in getRegState()
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| /llvm-project-15.0.7/llvm/test/TableGen/ |
| H A D | get-operand-type.td | 19 def RegOp : RegisterOperand<RegClass>;
42 let InOperandList = (ins RegOp:$x);
55 // CHECK-NEXT: RegClass, RegOp,
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| /llvm-project-15.0.7/llvm/lib/Target/BPF/MCTargetDesc/ |
| H A D | BPFInstPrinter.cpp | 68 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemOperand() local
72 assert(RegOp.isReg() && "Register operand not a register"); in printMemOperand()
73 O << getRegisterName(RegOp.getReg()); in printMemOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrFoldTables.h | 86 const X86MemoryFoldTableEntry *lookupTwoAddrFoldTable(unsigned RegOp);
90 const X86MemoryFoldTableEntry *lookupFoldTable(unsigned RegOp, unsigned OpNum);
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiAsmPrinter.cpp | 130 unsigned RegOp = OpNo + 1; in PrintAsmOperand() local
131 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
133 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /llvm-project-15.0.7/bolt/lib/Passes/ |
| H A D | JTFootprintReduction.cpp | 157 MCOperand RegOp = MCOperand::createReg(Reg); in tryOptimizeNonPIC() local
161 MCOperand::createReg(Index), Offset, RegOp); in tryOptimizeNonPIC()
195 MCOperand RegOp = MCOperand::createReg(BaseReg); in tryOptimizePIC() local
200 MCOperand::createReg(Index), JumpTableRef, RegOp); in tryOptimizePIC()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRMCCodeEmitter.cpp | 140 auto RegOp = MI.getOperand(OpNo); in encodeMemri() local
143 assert(RegOp.isReg() && "Expected register operand"); in encodeMemri()
147 switch (RegOp.getReg()) { in encodeMemri()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRAsmPrinter.cpp | 108 const MachineOperand &RegOp = MI->getOperand(OpNum); in PrintAsmOperand() local
110 assert(RegOp.isReg() && "Operand must be a register when you're" in PrintAsmOperand()
112 Register Reg = RegOp.getReg(); in PrintAsmOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.cpp | 585 unsigned RegOp = OpNum; in PrintAsmOperand() local
591 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; in PrintAsmOperand()
594 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; in PrintAsmOperand()
597 RegOp = OpNum + 1; in PrintAsmOperand()
599 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
601 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 1426 const MachineOperand *RegOp = nullptr; in isOMod() local
1432 RegOp = Src1; in isOMod()
1435 RegOp = Src0; in isOMod()
1447 return std::make_pair(RegOp, OMod); in isOMod()
1479 const MachineOperand *RegOp; in tryFoldOMod() local
1481 std::tie(RegOp, OMod) = isOMod(MI); in tryFoldOMod()
1482 if (OMod == SIOutMods::NONE || !RegOp->isReg() || in tryFoldOMod()
1483 RegOp->getSubReg() != AMDGPU::NoSubRegister || in tryFoldOMod()
1484 !MRI->hasOneNonDBGUser(RegOp->getReg())) in tryFoldOMod()
1487 MachineInstr *Def = MRI->getVRegDef(RegOp->getReg()); in tryFoldOMod()
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| H A D | SIInstrInfo.cpp | 1178 MachineOperand RegOp = Cond[1]; in insertVectorSelect() local
1179 RegOp.setImplicit(false); in insertVectorSelect()
1182 .add(RegOp); in insertVectorSelect()
1193 RegOp.setImplicit(false); in insertVectorSelect()
1196 .add(RegOp); in insertVectorSelect()
2257 Register Reg = RegOp.getReg(); in swapRegAndNonRegOperand()
2259 bool IsKill = RegOp.isKill(); in swapRegAndNonRegOperand()
2260 bool IsDead = RegOp.isDead(); in swapRegAndNonRegOperand()
2261 bool IsUndef = RegOp.isUndef(); in swapRegAndNonRegOperand()
2262 bool IsDebug = RegOp.isDebug(); in swapRegAndNonRegOperand()
[all …]
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| H A D | AMDGPUMachineCFGStructurizer.cpp | 1834 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); in createIfBlock() local
1835 ArrayRef<MachineOperand> Cond(RegOp); in createIfBlock()
2292 MachineOperand RegOp = in createIfRegion() local
2294 ArrayRef<MachineOperand> Cond(RegOp); in createIfRegion()
2351 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); in createIfRegion() local
2352 ArrayRef<MachineOperand> Cond(RegOp); in createIfRegion()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 887 const MCOperand &RegOp = MI->getOperand(OpNum); in printMatrix() local
888 assert(RegOp.isReg() && "Unexpected operand type!"); in printMatrix()
890 O << getRegisterName(RegOp.getReg()); in printMatrix()
918 const MCOperand &RegOp = MI->getOperand(OpNum); in printMatrixTileVector() local
919 assert(RegOp.isReg() && "Unexpected operand type!"); in printMatrixTileVector()
920 StringRef RegName = getRegisterName(RegOp.getReg()); in printMatrixTileVector()
931 const MCOperand &RegOp = MI->getOperand(OpNum); in printMatrixTile() local
932 assert(RegOp.isReg() && "Unexpected operand type!"); in printMatrixTile()
933 O << getRegisterName(RegOp.getReg()); in printMatrixTile()
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| /llvm-project-15.0.7/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 90 struct RegOp { struct
101 RegOp Reg;
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| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/AsmParser/ |
| H A D | LoongArchAsmParser.cpp | 99 struct RegOp { struct in __anon1ba74a0a0111::LoongArchOperand
110 struct RegOp Reg;
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 293 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg(); in collectUnprimedAccPHIs() local
294 if (!Register::isVirtualRegister(RegOp)) in collectUnprimedAccPHIs()
296 MachineInstr *Instr = MRI->getVRegDef(RegOp); in collectUnprimedAccPHIs()
339 Register RegOp = PHI->getOperand(PHIOp).getReg(); in convertUnprimedAccPHIs() local
340 MachineInstr *PHIInput = MRI->getVRegDef(RegOp); in convertUnprimedAccPHIs()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 1554 unsigned RegOp = CurOp++; in encodeInstruction() local
1561 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)), in encodeInstruction()
1567 unsigned RegOp = CurOp++; in encodeInstruction() local
1571 emitRegModRMByte(MI.getOperand(RegOp), 0, OS); in encodeInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 49 struct RegOp { struct
84 struct RegOp Reg;
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 395 MachineOperand &RegOp = PI.getOperand(i); in preprocessPhiNodes() local
396 if (RegOp.getSubReg() == 0) in preprocessPhiNodes()
406 .addReg(RegOp.getReg(), getRegState(RegOp), in preprocessPhiNodes()
407 RegOp.getSubReg()); in preprocessPhiNodes()
409 RegOp.setReg(NewReg); in preprocessPhiNodes()
410 RegOp.setSubReg(0); in preprocessPhiNodes()
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 122 struct RegOp { struct
139 struct RegOp Reg;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 398 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1; in PrintAsmOperand() local
399 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
401 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 245 struct RegOp { struct in __anon07e578c20211::SparcOperand
262 struct RegOp Reg;
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 109 struct RegOp { struct in __anon4f8b82ce0111::SystemZOperand
139 RegOp Reg;
|