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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-xcoff-funcsect.ll37 ; ASM: .csect .foo[PR],5
39 ; ASM-NEXT: .globl .foo[PR]
43 ; ASM-NEXT: .vbyte {{[0-9]+}}, .foo[PR]
46 ; ASM-NEXT: .csect .foo[PR],5
50 ; ASM: .csect .hidden_foo[PR],5
58 ; ASM-NEXT: .csect .hidden_foo[PR]
61 ; ASM: .csect .bar[PR],5
63 ; ASM-NEXT: .globl .bar[PR]
69 ; ASM-NEXT: .csect .bar[PR],5
71 ; ASM: bl .foo[PR]
[all …]
H A Daix-tls-gd-int.ll30 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
47 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
62 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
79 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
100 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
117 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
132 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
630 ; SMALL32: .extern .__tls_get_addr[PR]
631 ; SMALL64: .extern .__tls_get_addr[PR]
632 ; LARGE32: .extern .__tls_get_addr[PR]
[all …]
H A Daix-tls-gd-double.ll29 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
45 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
59 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
75 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
95 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
111 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
125 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
614 ; SMALL32: .extern .__tls_get_addr[PR]
615 ; SMALL64: .extern .__tls_get_addr[PR]
616 ; LARGE32: .extern .__tls_get_addr[PR]
[all …]
H A Daix-sret-param.ll42 ; MIR32-NEXT: BL_NOP <mcsymbol .foo[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implici…
48 ; MIR64-NEXT: BL8_NOP <mcsymbol .foo[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, impli…
56 ; ASM32-NEXT: bl .foo[PR]
62 ; ASM64-NEXT: bl .foo[PR]
75 ; MIR32-NEXT: BL_NOP <mcsymbol .bar[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implic…
81 ; MIR64-NEXT: BL8_NOP <mcsymbol .bar[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, impli…
89 ; ASM32-NEXT: bl .bar[PR]
96 ; ASM64-NEXT: bl .bar[PR]
H A Daix-tls-gd-longlong.ll31 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
50 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
66 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
83 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
105 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
124 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
140 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
670 ; SMALL32: .extern .__tls_get_addr[PR]
671 ; SMALL64: .extern .__tls_get_addr[PR]
672 ; LARGE32: .extern .__tls_get_addr[PR]
[all …]
H A Dpow-025-075-intrinsic-scalar-mass-afn.ll14 ; CHECK-AIX: bl .__xl_powf[PR]
28 ; CHECK-AIX: bl .__xl_pow[PR]
43 ; CHECK-AIX: bl .__xl_powf[PR]
57 ; CHECK-AIX: bl .__xl_pow[PR]
73 ; CHECK-AIX: bl .__xl_powf[PR]
89 ; CHECK-AIX: bl .__xl_pow[PR]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetMachine.cpp76 initializeX86PreTileConfigPass(PR); in LLVMInitializeX86Target()
77 initializeGlobalISel(PR); in LLVMInitializeX86Target()
78 initializeWinEHStatePassPass(PR); in LLVMInitializeX86Target()
79 initializeFixupBWInstPassPass(PR); in LLVMInitializeX86Target()
81 initializeFixupLEAPassPass(PR); in LLVMInitializeX86Target()
82 initializeFPSPass(PR); in LLVMInitializeX86Target()
86 initializeX86TileConfigPass(PR); in LLVMInitializeX86Target()
89 initializeX86LowerTileCopyPass(PR); in LLVMInitializeX86Target()
90 initializeX86ExpandPseudoPass(PR); in LLVMInitializeX86Target()
93 initializeX86AvoidSFBPassPass(PR); in LLVMInitializeX86Target()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyTargetMachine.cpp61 initializeFixFunctionBitcastsPass(PR); in LLVMInitializeWebAssemblyTarget()
62 initializeOptimizeReturnedPass(PR); in LLVMInitializeWebAssemblyTarget()
63 initializeWebAssemblyArgumentMovePass(PR); in LLVMInitializeWebAssemblyTarget()
68 initializeWebAssemblyRegStackifyPass(PR); in LLVMInitializeWebAssemblyTarget()
69 initializeWebAssemblyRegColoringPass(PR); in LLVMInitializeWebAssemblyTarget()
72 initializeWebAssemblyLateEHPreparePass(PR); in LLVMInitializeWebAssemblyTarget()
74 initializeWebAssemblyCFGSortPass(PR); in LLVMInitializeWebAssemblyTarget()
75 initializeWebAssemblyCFGStackifyPass(PR); in LLVMInitializeWebAssemblyTarget()
78 initializeWebAssemblyRegNumberingPass(PR); in LLVMInitializeWebAssemblyTarget()
79 initializeWebAssemblyDebugFixupPass(PR); in LLVMInitializeWebAssemblyTarget()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetMachine.cpp338 initializeR600PacketizerPass(*PR); in LLVMInitializeAMDGPUTarget()
341 initializeGlobalISel(*PR); in LLVMInitializeAMDGPUTarget()
343 initializeGCNDPPCombinePass(*PR); in LLVMInitializeAMDGPUTarget()
344 initializeSILowerI1CopiesPass(*PR); in LLVMInitializeAMDGPUTarget()
346 initializeSIFixSGPRCopiesPass(*PR); in LLVMInitializeAMDGPUTarget()
347 initializeSIFixVGPRCopiesPass(*PR); in LLVMInitializeAMDGPUTarget()
348 initializeSIFoldOperandsPass(*PR); in LLVMInitializeAMDGPUTarget()
349 initializeSIPeepholeSDWAPass(*PR); in LLVMInitializeAMDGPUTarget()
384 initializeSIModeRegisterPass(*PR); in LLVMInitializeAMDGPUTarget()
394 initializeGCNCreateVOPDPass(*PR); in LLVMInitializeAMDGPUTarget()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64TargetMachine.cpp201 initializeGlobalISel(*PR); in LLVMInitializeAArch64Target()
202 initializeAArch64A53Fix835769Pass(*PR); in LLVMInitializeAArch64Target()
206 initializeAArch64CollectLOHPass(*PR); in LLVMInitializeAArch64Target()
211 initializeAArch64ExpandPseudoPass(*PR); in LLVMInitializeAArch64Target()
212 initializeAArch64LoadStoreOptPass(*PR); in LLVMInitializeAArch64Target()
214 initializeAArch64SIMDInstrOptPass(*PR); in LLVMInitializeAArch64Target()
223 initializeFalkorHWPFFixPass(*PR); in LLVMInitializeAArch64Target()
225 initializeLDTLSCleanupPass(*PR); in LLVMInitializeAArch64Target()
226 initializeSVEIntrinsicOptsPass(*PR); in LLVMInitializeAArch64Target()
228 initializeAArch64SLSHardeningPass(*PR); in LLVMInitializeAArch64Target()
[all …]
/llvm-project-15.0.7/llvm/unittests/DebugInfo/CodeView/
H A DTypeHashingTest.cpp20 PointerRecord PR(TypeRecordKind::Pointer); in createPointerRecord() local
21 PR.setAttrs(PointerKind::Near32, PointerMode::Pointer, PointerOptions::None, in createPointerRecord()
23 PR.ReferentType = TI; in createPointerRecord()
24 return Builder.writeLeafType(PR); in createPointerRecord()
38 ProcedureRecord PR(TypeRecordKind::Procedure); in createProcedureRecord() local
39 PR.ArgumentList = ArgList; in createProcedureRecord()
40 PR.CallConv = CallingConvention::NearC; in createProcedureRecord()
41 PR.Options = FunctionOptions::None; in createProcedureRecord()
42 PR.ParameterCount = ParamCount; in createProcedureRecord()
43 PR.ReturnType = Return; in createProcedureRecord()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetMachine.cpp117 initializePPCCTRLoopsVerifyPass(PR); in LLVMInitializePowerPCTarget()
120 initializePPCTOCRegDepsPass(PR); in LLVMInitializePowerPCTarget()
121 initializePPCEarlyReturnPass(PR); in LLVMInitializePowerPCTarget()
122 initializePPCVSXCopyPass(PR); in LLVMInitializePowerPCTarget()
123 initializePPCVSXFMAMutatePass(PR); in LLVMInitializePowerPCTarget()
126 initializePPCBSelPass(PR); in LLVMInitializePowerPCTarget()
128 initializePPCBoolRetToIntPass(PR); in LLVMInitializePowerPCTarget()
129 initializePPCExpandISELPass(PR); in LLVMInitializePowerPCTarget()
132 initializePPCMIPeepholePass(PR); in LLVMInitializePowerPCTarget()
136 initializeGlobalISel(PR); in LLVMInitializePowerPCTarget()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonTargetMachine.cpp205 initializeHexagonBitSimplifyPass(PR); in LLVMInitializeHexagonTarget()
206 initializeHexagonConstExtendersPass(PR); in LLVMInitializeHexagonTarget()
208 initializeHexagonCopyToCombinePass(PR); in LLVMInitializeHexagonTarget()
210 initializeHexagonGenMuxPass(PR); in LLVMInitializeHexagonTarget()
211 initializeHexagonHardwareLoopsPass(PR); in LLVMInitializeHexagonTarget()
213 initializeHexagonNewValueJumpPass(PR); in LLVMInitializeHexagonTarget()
214 initializeHexagonOptAddrModePass(PR); in LLVMInitializeHexagonTarget()
215 initializeHexagonPacketizerPass(PR); in LLVMInitializeHexagonTarget()
216 initializeHexagonRDFOptPass(PR); in LLVMInitializeHexagonTarget()
217 initializeHexagonSplitDoubleRegsPass(PR); in LLVMInitializeHexagonTarget()
[all …]
H A DHexagonGenPredicate.cpp77 raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR)
79 raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) { in operator <<() argument
80 return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S); in operator <<()
259 RegisterSubReg PR = DefI->getOperand(1); in getPredRegFor() local
260 G2P.insert(std::make_pair(Reg, PR)); in getPredRegFor()
262 return PR; in getPredRegFor()
326 RegisterSubReg PR = WorkQ.front(); in isScalarPred() local
328 const MachineInstr *DefI = MRI->getVRegDef(PR.R); in isScalarPred()
335 if (MRI->getRegClass(PR.R) != PredRC) in isScalarPred()
404 RegisterSubReg PR = getPredRegFor(MI->getOperand(1)); in convertToPredForm() local
[all …]
H A DHexagonGenMux.cpp112 MuxInfo(MachineBasicBlock::iterator It, unsigned DR, unsigned PR, in MuxInfo()
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
245 Register PR = PredOp.getReg(); in genMuxInBlock() local
252 if (F != CM.end() && F->second.PredR != PR) { in genMuxInBlock()
259 F->second.PredR = PR; in genMuxInBlock()
283 if (!DU.Defs[PR]) in genMuxInBlock()
307 if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) { in genMuxInBlock()
324 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2)); in genMuxInBlock()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFTargetMachine.cpp43 PassRegistry &PR = *PassRegistry::getPassRegistry(); in LLVMInitializeBPFTarget() local
44 initializeBPFAbstractMemberAccessLegacyPassPass(PR); in LLVMInitializeBPFTarget()
45 initializeBPFPreserveDITypePass(PR); in LLVMInitializeBPFTarget()
46 initializeBPFIRPeepholePass(PR); in LLVMInitializeBPFTarget()
47 initializeBPFAdjustOptPass(PR); in LLVMInitializeBPFTarget()
48 initializeBPFCheckAndAdjustIRPass(PR); in LLVMInitializeBPFTarget()
49 initializeBPFMIPeepholePass(PR); in LLVMInitializeBPFTarget()
50 initializeBPFMIPeepholeTruncElimPass(PR); in LLVMInitializeBPFTarget()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXTargetMachine.cpp86 PassRegistry &PR = *PassRegistry::getPassRegistry(); in LLVMInitializeNVPTXTarget() local
87 initializeNVVMReflectPass(PR); in LLVMInitializeNVPTXTarget()
88 initializeNVVMIntrRangePass(PR); in LLVMInitializeNVPTXTarget()
89 initializeGenericToNVVMPass(PR); in LLVMInitializeNVPTXTarget()
90 initializeNVPTXAllocaHoistingPass(PR); in LLVMInitializeNVPTXTarget()
91 initializeNVPTXAssignValidGlobalNamesPass(PR); in LLVMInitializeNVPTXTarget()
92 initializeNVPTXAtomicLowerPass(PR); in LLVMInitializeNVPTXTarget()
93 initializeNVPTXLowerArgsPass(PR); in LLVMInitializeNVPTXTarget()
94 initializeNVPTXLowerAllocaPass(PR); in LLVMInitializeNVPTXTarget()
95 initializeNVPTXLowerAggrCopiesPass(PR); in LLVMInitializeNVPTXTarget()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVTargetMachine.cpp48 auto *PR = PassRegistry::getPassRegistry(); in LLVMInitializeRISCVTarget() local
49 initializeGlobalISel(*PR); in LLVMInitializeRISCVTarget()
50 initializeRISCVMakeCompressibleOptPass(*PR); in LLVMInitializeRISCVTarget()
51 initializeRISCVGatherScatterLoweringPass(*PR); in LLVMInitializeRISCVTarget()
52 initializeRISCVCodeGenPreparePass(*PR); in LLVMInitializeRISCVTarget()
53 initializeRISCVMergeBaseOffsetOptPass(*PR); in LLVMInitializeRISCVTarget()
54 initializeRISCVSExtWRemovalPass(*PR); in LLVMInitializeRISCVTarget()
55 initializeRISCVExpandPseudoPass(*PR); in LLVMInitializeRISCVTarget()
56 initializeRISCVInsertVSETVLIPass(*PR); in LLVMInitializeRISCVTarget()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZTargetMachine.cpp35 auto &PR = *PassRegistry::getPassRegistry(); in LLVMInitializeSystemZTarget() local
36 initializeSystemZElimComparePass(PR); in LLVMInitializeSystemZTarget()
37 initializeSystemZShortenInstPass(PR); in LLVMInitializeSystemZTarget()
38 initializeSystemZLongBranchPass(PR); in LLVMInitializeSystemZTarget()
39 initializeSystemZLDCleanupPass(PR); in LLVMInitializeSystemZTarget()
40 initializeSystemZShortenInstPass(PR); in LLVMInitializeSystemZTarget()
41 initializeSystemZPostRewritePass(PR); in LLVMInitializeSystemZTarget()
42 initializeSystemZTDCPassPass(PR); in LLVMInitializeSystemZTarget()
/llvm-project-15.0.7/llvm/lib/Target/DirectX/
H A DDirectXTargetMachine.cpp37 auto *PR = PassRegistry::getPassRegistry(); in LLVMInitializeDirectXTarget() local
38 initializeDXILPrepareModulePass(*PR); in LLVMInitializeDirectXTarget()
39 initializeEmbedDXILPassPass(*PR); in LLVMInitializeDirectXTarget()
40 initializeDXILOpLoweringLegacyPass(*PR); in LLVMInitializeDirectXTarget()
41 initializeDXILTranslateMetadataPass(*PR); in LLVMInitializeDirectXTarget()
/llvm-project-15.0.7/clang/include/clang/Lex/
H A DPreprocessingRecord.h43 void *operator new(size_t bytes, clang::PreprocessingRecord &PR,
47 void operator delete(void *ptr, clang::PreprocessingRecord &PR,
112 void *operator new(size_t bytes, PreprocessingRecord &PR,
114 return ::operator new(bytes, PR, alignment);
119 void operator delete(void *ptr, PreprocessingRecord &PR, in delete() argument
121 return ::operator delete(ptr, PR, alignment); in delete()
569 inline void *operator new(size_t bytes, clang::PreprocessingRecord &PR, in new() argument
571 return PR.Allocate(bytes, alignment); in new()
574 inline void operator delete(void *ptr, clang::PreprocessingRecord &PR, in delete() argument
576 PR.Deallocate(ptr); in delete()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsTargetMachine.cpp61 PassRegistry *PR = PassRegistry::getPassRegistry(); in LLVMInitializeMipsTarget() local
62 initializeGlobalISel(*PR); in LLVMInitializeMipsTarget()
63 initializeMipsDelaySlotFillerPass(*PR); in LLVMInitializeMipsTarget()
64 initializeMipsBranchExpansionPass(*PR); in LLVMInitializeMipsTarget()
65 initializeMicroMipsSizeReducePass(*PR); in LLVMInitializeMipsTarget()
66 initializeMipsPreLegalizerCombinerPass(*PR); in LLVMInitializeMipsTarget()
67 initializeMipsPostLegalizerCombinerPass(*PR); in LLVMInitializeMipsTarget()
68 initializeMipsMulMulBugFixPass(*PR); in LLVMInitializeMipsTarget()
/llvm-project-15.0.7/libunwind/src/
H A Dassembly.h219 .csect .text[PR], 2 SEPARATOR \
220 .csect .name[PR], 2 SEPARATOR \
222 .globl .name[PR] SEPARATOR \
226 .vbyte VBYTE_LEN, .name[PR] SEPARATOR \
231 .csect .name[PR], 2 SEPARATOR \
254 .csect .text[PR], 2 SEPARATOR \
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRTargetMachine.cpp93 auto &PR = *PassRegistry::getPassRegistry(); in LLVMInitializeAVRTarget() local
94 initializeAVRExpandPseudoPass(PR); in LLVMInitializeAVRTarget()
95 initializeAVRShiftExpandPass(PR); in LLVMInitializeAVRTarget()
/llvm-project-15.0.7/llvm/test/DebugInfo/XCOFF/
H A Dfunction-sections.ll40 ; CHECK: .csect .text[PR],5
42 ; CHECK-NEXT: .csect .foo[PR],5
44 ; CHECK-NEXT: .globl .foo[PR]
47 ; CHECK-NEXT: .vbyte 4, .foo[PR] # @foo
50 ; CHECK-NEXT: .csect .foo[PR],5
73 ; CHECK-NEXT: .vbyte 4, L..foo0-.foo[PR] # Function size
78 ; CHECK-NEXT: .csect .bar[PR],5
80 ; CHECK-NEXT: .globl .bar[PR]
83 ; CHECK-NEXT: .vbyte 4, .bar[PR] # @bar
86 ; CHECK-NEXT: .csect .bar[PR],5
[all …]

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