1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "PPCTargetMachine.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "PPC.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCMacroFusion.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetObjectFile.h"
20 #include "PPCTargetTransformInfo.h"
21 #include "TargetInfo/PowerPCTargetInfo.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/Analysis/TargetTransformInfo.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
30 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
31 #include "llvm/CodeGen/GlobalISel/Localizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/MachineScheduler.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/InitializePasses.h"
40 #include "llvm/MC/TargetRegistry.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Target/TargetLoweringObjectFile.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include <cassert>
48 #include <memory>
49 #include <string>
50
51 using namespace llvm;
52
53
54 static cl::opt<bool>
55 EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
56 cl::desc("enable coalescing of duplicate branches for PPC"));
57 static cl::
58 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
59 cl::desc("Disable CTR loops for PPC"));
60
61 static cl::
62 opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden,
63 cl::desc("Disable PPC loop instr form prep"));
64
65 static cl::opt<bool>
66 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
67 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
68
69 static cl::
70 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
71 cl::desc("Disable VSX Swap Removal for PPC"));
72
73 static cl::
74 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
75 cl::desc("Disable machine peepholes for PPC"));
76
77 static cl::opt<bool>
78 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
79 cl::desc("Enable optimizations on complex GEPs"),
80 cl::init(true));
81
82 static cl::opt<bool>
83 EnablePrefetch("enable-ppc-prefetching",
84 cl::desc("enable software prefetching on PPC"),
85 cl::init(false), cl::Hidden);
86
87 static cl::opt<bool>
88 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
89 cl::desc("Add extra TOC register dependencies"),
90 cl::init(true), cl::Hidden);
91
92 static cl::opt<bool>
93 EnableMachineCombinerPass("ppc-machine-combiner",
94 cl::desc("Enable the machine combiner pass"),
95 cl::init(true), cl::Hidden);
96
97 static cl::opt<bool>
98 ReduceCRLogical("ppc-reduce-cr-logicals",
99 cl::desc("Expand eligible cr-logical binary ops to branches"),
100 cl::init(true), cl::Hidden);
101
102 static cl::opt<bool> EnablePPCGenScalarMASSEntries(
103 "enable-ppc-gen-scalar-mass", cl::init(false),
104 cl::desc("Enable lowering math functions to their corresponding MASS "
105 "(scalar) entries"),
106 cl::Hidden);
107
LLVMInitializePowerPCTarget()108 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() {
109 // Register the targets
110 RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
111 RegisterTargetMachine<PPCTargetMachine> B(getThePPC32LETarget());
112 RegisterTargetMachine<PPCTargetMachine> C(getThePPC64Target());
113 RegisterTargetMachine<PPCTargetMachine> D(getThePPC64LETarget());
114
115 PassRegistry &PR = *PassRegistry::getPassRegistry();
116 #ifndef NDEBUG
117 initializePPCCTRLoopsVerifyPass(PR);
118 #endif
119 initializePPCLoopInstrFormPrepPass(PR);
120 initializePPCTOCRegDepsPass(PR);
121 initializePPCEarlyReturnPass(PR);
122 initializePPCVSXCopyPass(PR);
123 initializePPCVSXFMAMutatePass(PR);
124 initializePPCVSXSwapRemovalPass(PR);
125 initializePPCReduceCRLogicalsPass(PR);
126 initializePPCBSelPass(PR);
127 initializePPCBranchCoalescingPass(PR);
128 initializePPCBoolRetToIntPass(PR);
129 initializePPCExpandISELPass(PR);
130 initializePPCPreEmitPeepholePass(PR);
131 initializePPCTLSDynamicCallPass(PR);
132 initializePPCMIPeepholePass(PR);
133 initializePPCLowerMASSVEntriesPass(PR);
134 initializePPCGenScalarMASSEntriesPass(PR);
135 initializePPCExpandAtomicPseudoPass(PR);
136 initializeGlobalISel(PR);
137 initializePPCCTRLoopsPass(PR);
138 }
139
isLittleEndianTriple(const Triple & T)140 static bool isLittleEndianTriple(const Triple &T) {
141 return T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppcle;
142 }
143
144 /// Return the datalayout string of a subtarget.
getDataLayoutString(const Triple & T)145 static std::string getDataLayoutString(const Triple &T) {
146 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
147 std::string Ret;
148
149 // Most PPC* platforms are big endian, PPC(64)LE is little endian.
150 if (isLittleEndianTriple(T))
151 Ret = "e";
152 else
153 Ret = "E";
154
155 Ret += DataLayout::getManglingComponent(T);
156
157 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
158 // pointers.
159 if (!is64Bit || T.getOS() == Triple::Lv2)
160 Ret += "-p:32:32";
161
162 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
163 // documentation are wrong; these are correct (i.e. "what gcc does").
164 Ret += "-i64:64";
165
166 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
167 if (is64Bit)
168 Ret += "-n32:64";
169 else
170 Ret += "-n32";
171
172 // Specify the vector alignment explicitly. For v256i1 and v512i1, the
173 // calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
174 // which is 256 and 512 bytes - way over aligned.
175 if (is64Bit && (T.isOSAIX() || T.isOSLinux()))
176 Ret += "-S128-v256:256:256-v512:512:512";
177
178 return Ret;
179 }
180
computeFSAdditions(StringRef FS,CodeGenOpt::Level OL,const Triple & TT)181 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
182 const Triple &TT) {
183 std::string FullFS = std::string(FS);
184
185 // Make sure 64-bit features are available when CPUname is generic
186 if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
187 if (!FullFS.empty())
188 FullFS = "+64bit," + FullFS;
189 else
190 FullFS = "+64bit";
191 }
192
193 if (OL >= CodeGenOpt::Default) {
194 if (!FullFS.empty())
195 FullFS = "+crbits," + FullFS;
196 else
197 FullFS = "+crbits";
198 }
199
200 if (OL != CodeGenOpt::None) {
201 if (!FullFS.empty())
202 FullFS = "+invariant-function-descriptors," + FullFS;
203 else
204 FullFS = "+invariant-function-descriptors";
205 }
206
207 if (TT.isOSAIX()) {
208 if (!FullFS.empty())
209 FullFS = "+aix," + FullFS;
210 else
211 FullFS = "+aix";
212 }
213
214 return FullFS;
215 }
216
createTLOF(const Triple & TT)217 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
218 if (TT.isOSAIX())
219 return std::make_unique<TargetLoweringObjectFileXCOFF>();
220
221 return std::make_unique<PPC64LinuxTargetObjectFile>();
222 }
223
computeTargetABI(const Triple & TT,const TargetOptions & Options)224 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
225 const TargetOptions &Options) {
226 if (Options.MCOptions.getABIName().startswith("elfv1"))
227 return PPCTargetMachine::PPC_ABI_ELFv1;
228 else if (Options.MCOptions.getABIName().startswith("elfv2"))
229 return PPCTargetMachine::PPC_ABI_ELFv2;
230
231 assert(Options.MCOptions.getABIName().empty() &&
232 "Unknown target-abi option!");
233
234 if (TT.isMacOSX())
235 return PPCTargetMachine::PPC_ABI_UNKNOWN;
236
237 switch (TT.getArch()) {
238 case Triple::ppc64le:
239 return PPCTargetMachine::PPC_ABI_ELFv2;
240 case Triple::ppc64:
241 return PPCTargetMachine::PPC_ABI_ELFv1;
242 default:
243 return PPCTargetMachine::PPC_ABI_UNKNOWN;
244 }
245 }
246
getEffectiveRelocModel(const Triple & TT,Optional<Reloc::Model> RM)247 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
248 Optional<Reloc::Model> RM) {
249 assert((!TT.isOSAIX() || !RM || *RM == Reloc::PIC_) &&
250 "Invalid relocation model for AIX.");
251
252 if (RM)
253 return *RM;
254
255 // Big Endian PPC and AIX default to PIC.
256 if (TT.getArch() == Triple::ppc64 || TT.isOSAIX())
257 return Reloc::PIC_;
258
259 // Rest are static by default.
260 return Reloc::Static;
261 }
262
getEffectivePPCCodeModel(const Triple & TT,Optional<CodeModel::Model> CM,bool JIT)263 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
264 Optional<CodeModel::Model> CM,
265 bool JIT) {
266 if (CM) {
267 if (*CM == CodeModel::Tiny)
268 report_fatal_error("Target does not support the tiny CodeModel", false);
269 if (*CM == CodeModel::Kernel)
270 report_fatal_error("Target does not support the kernel CodeModel", false);
271 return *CM;
272 }
273
274 if (JIT)
275 return CodeModel::Small;
276 if (TT.isOSAIX())
277 return CodeModel::Small;
278
279 assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based.");
280
281 if (TT.isArch32Bit())
282 return CodeModel::Small;
283
284 assert(TT.isArch64Bit() && "Unsupported PPC architecture.");
285 return CodeModel::Medium;
286 }
287
288
createPPCMachineScheduler(MachineSchedContext * C)289 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
290 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
291 ScheduleDAGMILive *DAG =
292 new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
293 std::make_unique<PPCPreRASchedStrategy>(C) :
294 std::make_unique<GenericScheduler>(C));
295 // add DAG Mutations here.
296 DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
297 if (ST.hasStoreFusion())
298 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
299 if (ST.hasFusion())
300 DAG->addMutation(createPowerPCMacroFusionDAGMutation());
301
302 return DAG;
303 }
304
createPPCPostMachineScheduler(MachineSchedContext * C)305 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
306 MachineSchedContext *C) {
307 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
308 ScheduleDAGMI *DAG =
309 new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
310 std::make_unique<PPCPostRASchedStrategy>(C) :
311 std::make_unique<PostGenericScheduler>(C), true);
312 // add DAG Mutations here.
313 if (ST.hasStoreFusion())
314 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
315 if (ST.hasFusion())
316 DAG->addMutation(createPowerPCMacroFusionDAGMutation());
317 return DAG;
318 }
319
320 // The FeatureString here is a little subtle. We are modifying the feature
321 // string with what are (currently) non-function specific overrides as it goes
322 // into the LLVMTargetMachine constructor and then using the stored value in the
323 // Subtarget constructor below it.
PPCTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)324 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
325 StringRef CPU, StringRef FS,
326 const TargetOptions &Options,
327 Optional<Reloc::Model> RM,
328 Optional<CodeModel::Model> CM,
329 CodeGenOpt::Level OL, bool JIT)
330 : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
331 computeFSAdditions(FS, OL, TT), Options,
332 getEffectiveRelocModel(TT, RM),
333 getEffectivePPCCodeModel(TT, CM, JIT), OL),
334 TLOF(createTLOF(getTargetTriple())),
335 TargetABI(computeTargetABI(TT, Options)),
336 Endianness(isLittleEndianTriple(TT) ? Endian::LITTLE : Endian::BIG) {
337 initAsmInfo();
338 }
339
340 PPCTargetMachine::~PPCTargetMachine() = default;
341
342 const PPCSubtarget *
getSubtargetImpl(const Function & F) const343 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
344 Attribute CPUAttr = F.getFnAttribute("target-cpu");
345 Attribute FSAttr = F.getFnAttribute("target-features");
346
347 std::string CPU =
348 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
349 std::string FS =
350 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
351
352 // FIXME: This is related to the code below to reset the target options,
353 // we need to know whether or not the soft float flag is set on the
354 // function before we can generate a subtarget. We also need to use
355 // it as a key for the subtarget since that can be the only difference
356 // between two functions.
357 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
358 // If the soft float attribute is set on the function turn on the soft float
359 // subtarget feature.
360 if (SoftFloat)
361 FS += FS.empty() ? "-hard-float" : ",-hard-float";
362
363 auto &I = SubtargetMap[CPU + FS];
364 if (!I) {
365 // This needs to be done before we create a new subtarget since any
366 // creation will depend on the TM and the code generation flags on the
367 // function that reside in TargetOptions.
368 resetTargetOptions(F);
369 I = std::make_unique<PPCSubtarget>(
370 TargetTriple, CPU,
371 // FIXME: It would be good to have the subtarget additions here
372 // not necessary. Anything that turns them on/off (overrides) ends
373 // up being put at the end of the feature string, but the defaults
374 // shouldn't require adding them. Fixing this means pulling Feature64Bit
375 // out of most of the target cpus in the .td file and making it set only
376 // as part of initialization via the TargetTriple.
377 computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
378 }
379 return I.get();
380 }
381
382 //===----------------------------------------------------------------------===//
383 // Pass Pipeline Configuration
384 //===----------------------------------------------------------------------===//
385
386 namespace {
387
388 /// PPC Code Generator Pass Configuration Options.
389 class PPCPassConfig : public TargetPassConfig {
390 public:
PPCPassConfig(PPCTargetMachine & TM,PassManagerBase & PM)391 PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
392 : TargetPassConfig(TM, PM) {
393 // At any optimization level above -O0 we use the Machine Scheduler and not
394 // the default Post RA List Scheduler.
395 if (TM.getOptLevel() != CodeGenOpt::None)
396 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
397 }
398
getPPCTargetMachine() const399 PPCTargetMachine &getPPCTargetMachine() const {
400 return getTM<PPCTargetMachine>();
401 }
402
403 void addIRPasses() override;
404 bool addPreISel() override;
405 bool addILPOpts() override;
406 bool addInstSelector() override;
407 void addMachineSSAOptimization() override;
408 void addPreRegAlloc() override;
409 void addPreSched2() override;
410 void addPreEmitPass() override;
411 void addPreEmitPass2() override;
412 // GlobalISEL
413 bool addIRTranslator() override;
414 bool addLegalizeMachineIR() override;
415 bool addRegBankSelect() override;
416 bool addGlobalInstructionSelect() override;
417
418 ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext * C) const419 createMachineScheduler(MachineSchedContext *C) const override {
420 return createPPCMachineScheduler(C);
421 }
422 ScheduleDAGInstrs *
createPostMachineScheduler(MachineSchedContext * C) const423 createPostMachineScheduler(MachineSchedContext *C) const override {
424 return createPPCPostMachineScheduler(C);
425 }
426 };
427
428 } // end anonymous namespace
429
createPassConfig(PassManagerBase & PM)430 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
431 return new PPCPassConfig(*this, PM);
432 }
433
addIRPasses()434 void PPCPassConfig::addIRPasses() {
435 if (TM->getOptLevel() != CodeGenOpt::None)
436 addPass(createPPCBoolRetToIntPass());
437 addPass(createAtomicExpandPass());
438
439 // Lower generic MASSV routines to PowerPC subtarget-specific entries.
440 addPass(createPPCLowerMASSVEntriesPass());
441
442 // Generate PowerPC target-specific entries for scalar math functions
443 // that are available in IBM MASS (scalar) library.
444 if (TM->getOptLevel() == CodeGenOpt::Aggressive &&
445 EnablePPCGenScalarMASSEntries) {
446 TM->Options.PPCGenScalarMASSEntries = EnablePPCGenScalarMASSEntries;
447 addPass(createPPCGenScalarMASSEntriesPass());
448 }
449
450 // If explicitly requested, add explicit data prefetch intrinsics.
451 if (EnablePrefetch.getNumOccurrences() > 0)
452 addPass(createLoopDataPrefetchPass());
453
454 if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
455 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
456 // and lower a GEP with multiple indices to either arithmetic operations or
457 // multiple GEPs with single index.
458 addPass(createSeparateConstOffsetFromGEPPass(true));
459 // Call EarlyCSE pass to find and remove subexpressions in the lowered
460 // result.
461 addPass(createEarlyCSEPass());
462 // Do loop invariant code motion in case part of the lowered result is
463 // invariant.
464 addPass(createLICMPass());
465 }
466
467 TargetPassConfig::addIRPasses();
468 }
469
addPreISel()470 bool PPCPassConfig::addPreISel() {
471 if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::None)
472 addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine()));
473
474 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
475 addPass(createHardwareLoopsPass());
476
477 return false;
478 }
479
addILPOpts()480 bool PPCPassConfig::addILPOpts() {
481 addPass(&EarlyIfConverterID);
482
483 if (EnableMachineCombinerPass)
484 addPass(&MachineCombinerID);
485
486 return true;
487 }
488
addInstSelector()489 bool PPCPassConfig::addInstSelector() {
490 // Install an instruction selector.
491 addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
492
493 #ifndef NDEBUG
494 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
495 addPass(createPPCCTRLoopsVerify());
496 #endif
497
498 addPass(createPPCVSXCopyPass());
499 return false;
500 }
501
addMachineSSAOptimization()502 void PPCPassConfig::addMachineSSAOptimization() {
503 // PPCBranchCoalescingPass need to be done before machine sinking
504 // since it merges empty blocks.
505 if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
506 addPass(createPPCBranchCoalescingPass());
507 TargetPassConfig::addMachineSSAOptimization();
508 // For little endian, remove where possible the vector swap instructions
509 // introduced at code generation to normalize vector element order.
510 if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
511 !DisableVSXSwapRemoval)
512 addPass(createPPCVSXSwapRemovalPass());
513 // Reduce the number of cr-logical ops.
514 if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
515 addPass(createPPCReduceCRLogicalsPass());
516 // Target-specific peephole cleanups performed after instruction
517 // selection.
518 if (!DisableMIPeephole) {
519 addPass(createPPCMIPeepholePass());
520 addPass(&DeadMachineInstructionElimID);
521 }
522 }
523
addPreRegAlloc()524 void PPCPassConfig::addPreRegAlloc() {
525 if (getOptLevel() != CodeGenOpt::None) {
526 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
527 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
528 &PPCVSXFMAMutateID);
529 }
530
531 // FIXME: We probably don't need to run these for -fPIE.
532 if (getPPCTargetMachine().isPositionIndependent()) {
533 // FIXME: LiveVariables should not be necessary here!
534 // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
535 // LiveVariables. This (unnecessary) dependency has been removed now,
536 // however a stage-2 clang build fails without LiveVariables computed here.
537 addPass(&LiveVariablesID);
538 addPass(createPPCTLSDynamicCallPass());
539 }
540 if (EnableExtraTOCRegDeps)
541 addPass(createPPCTOCRegDepsPass());
542
543 // Run CTR loops pass before MachinePipeliner pass.
544 // MachinePipeliner will pipeline all instructions before the terminator, but
545 // we don't want DecreaseCTRPseudo to be pipelined.
546 // Note we may lose some MachinePipeliner opportunities if we run CTR loops
547 // generation pass before MachinePipeliner and the loop is converted back to
548 // a normal loop. We can revisit this later for running PPCCTRLoops after
549 // MachinePipeliner and handling DecreaseCTRPseudo in MachinePipeliner pass.
550 if (getOptLevel() != CodeGenOpt::None)
551 addPass(createPPCCTRLoopsPass());
552
553 if (getOptLevel() != CodeGenOpt::None)
554 addPass(&MachinePipelinerID);
555 }
556
addPreSched2()557 void PPCPassConfig::addPreSched2() {
558 if (getOptLevel() != CodeGenOpt::None)
559 addPass(&IfConverterID);
560 }
561
addPreEmitPass()562 void PPCPassConfig::addPreEmitPass() {
563 addPass(createPPCPreEmitPeepholePass());
564 addPass(createPPCExpandISELPass());
565
566 if (getOptLevel() != CodeGenOpt::None)
567 addPass(createPPCEarlyReturnPass());
568 }
569
addPreEmitPass2()570 void PPCPassConfig::addPreEmitPass2() {
571 // Schedule the expansion of AMOs at the last possible moment, avoiding the
572 // possibility for other passes to break the requirements for forward
573 // progress in the LL/SC block.
574 addPass(createPPCExpandAtomicPseudoPass());
575 // Must run branch selection immediately preceding the asm printer.
576 addPass(createPPCBranchSelectionPass());
577 }
578
579 TargetTransformInfo
getTargetTransformInfo(const Function & F) const580 PPCTargetMachine::getTargetTransformInfo(const Function &F) const {
581 return TargetTransformInfo(PPCTTIImpl(this, F));
582 }
583
isLittleEndian() const584 bool PPCTargetMachine::isLittleEndian() const {
585 assert(Endianness != Endian::NOT_DETECTED &&
586 "Unable to determine endianness");
587 return Endianness == Endian::LITTLE;
588 }
589
590 static MachineSchedRegistry
591 PPCPreRASchedRegistry("ppc-prera",
592 "Run PowerPC PreRA specific scheduler",
593 createPPCMachineScheduler);
594
595 static MachineSchedRegistry
596 PPCPostRASchedRegistry("ppc-postra",
597 "Run PowerPC PostRA specific scheduler",
598 createPPCPostMachineScheduler);
599
600 // Global ISEL
addIRTranslator()601 bool PPCPassConfig::addIRTranslator() {
602 addPass(new IRTranslator());
603 return false;
604 }
605
addLegalizeMachineIR()606 bool PPCPassConfig::addLegalizeMachineIR() {
607 addPass(new Legalizer());
608 return false;
609 }
610
addRegBankSelect()611 bool PPCPassConfig::addRegBankSelect() {
612 addPass(new RegBankSelect());
613 return false;
614 }
615
addGlobalInstructionSelect()616 bool PPCPassConfig::addGlobalInstructionSelect() {
617 addPass(new InstructionSelect(getOptLevel()));
618 return false;
619 }
620